公开(公告)号：US20050151227A1

公开(公告)日：2005-07-14

申请号：US10753826

申请日：2004-01-08

申请人： Yu-Huei Chen ,  Sung-Ming Jang ,  Chen-Hua Yu

发明人： Yu-Huei Chen ,  Sung-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L21/3105 ,  H01L23/544

CPC分类号： H01L21/31053

摘要： In accordance with the objectives of the invention a new method is provided to tune the Edge Bead Remove hump and to further prevent a pointed or tip shaped Edge Bead Remove edge, thus preventing peeling of the low-k dielectric film after the process of Chemical Mechanical Polishing of the low-k film.

摘要翻译： 根据本发明的目的，提供了一种新的方法来调节边缘珠移除隆起并进一步防止尖端或尖端形状的边缘去除边缘，从而防止化学机械过程之后的低k电介质膜的剥离 抛光低k电影。

公开(公告)号：US20050077627A1

公开(公告)日：2005-04-14

申请号：US10684224

申请日：2003-10-10

申请人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Chenming Hu ,  Chao-Hsiung Wang

发明人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Chenming Hu ,  Chao-Hsiung Wang

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of forming the semiconductor devices using an HTS (High Temperature Superconductor) layer in combination with a typical diffusion layer between the dielectric material and the copper (or other metal) conductive wiring. The HTS layer includes a superconductor material comprised of barium copper oxide and a rare earth element. The rare earth element yttrium is particularly suitable. For semiconductor devices having other semiconductor circuits or elements above the wiring, a capping layer of HTS material is deposited over the wiring before a cover layer of dielectric is deposited.

摘要翻译： 使用HTS（高温超导体）层与介电材料和铜（或其它金属）导电布线之间的典型扩散层组合形成半导体器件的半导体器件和方法。 HTS层包括由氧化钡钡和稀土元素构成的超导体材料。 稀土元素钇特别适合。 对于具有其它半导体电路或布线之上的元件的半导体器件，在沉积覆盖层的电介质之前，在布线上沉积HTS材料的覆盖层。

公开(公告)号：US06764959B2

公开(公告)日：2004-07-20

申请号：US09920911

申请日：2001-08-02

申请人： Mo-Chiun Yu ,  Shih-Chang Chen ,  Chen-Hua Yu

发明人： Mo-Chiun Yu ,  Shih-Chang Chen ,  Chen-Hua Yu

IPC分类号： H01L2100

CPC分类号： H01L21/823462 ,  Y10S438/981

摘要： Within a sequential and repetitive thermal oxidation and stripping method for forming a plurality of gate dielectric layers having a maximum numbered plurality of thicknesses upon a semiconductor substrate, there is provided a compensating thermal annealing when forming less than the maximum numbered plurality of thicknesses of the plurality of gate dielectric layers upon the semiconductor substrate. By employing the compensating thermal annealing, the semiconductor substrate is more readily manufacturable in conjunction with related microelectronic fabrications.

摘要翻译： 在用于在半导体衬底上形成具有最大数量的多个厚度的多个栅极电介质层的连续且重复的热氧化和剥离方法中，提供了当形成小于多个厚度的最大数量的多个厚度时的补偿热退火 的栅极电介质层。 通过采用补偿热退火，半导体衬底更容易与相关的微电子制造结合起来制造。

公开(公告)号：US06706637B2

公开(公告)日：2004-03-16

申请号：US10143700

申请日：2002-05-09

申请人： Yu-Huei Chen ,  Yao-Yi Cheng ,  Sung-Ming Jang ,  Chen-Hua Yu

发明人： Yu-Huei Chen ,  Yao-Yi Cheng ,  Sung-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L21311

CPC分类号： H01L21/76826 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76822

摘要： Within a method for forming a dual damascene aperture there is surface treated a first dielectric layer to form a surface treated first dielectric layer having a first surface composition different than a first bulk composition. There is then formed upon the surface treated first dielectric layer a second dielectric layer having a second bulk composition. Finally, there is then formed through the second dielectric layer a trench contiguous with and overlapping a via formed through the surface treated first dielectric layer. Within the present invention, when forming the trench through the second dielectric layer an endpoint is determined by detecting a difference between the second bulk composition and the first surface composition.

摘要翻译： 在用于形成双镶嵌孔的方法中，表面处理了第一介电层，以形成具有不同于第一块体组合物的第一表面组成的经表面处理的第一介电层。 然后在表面处理的第一电介质层上形成具有第二体积组成的第二电介质层。 最后，然后通过第二电介质层形成与通过经表面处理的第一介电层形成的通孔相邻并与其重叠的沟槽。 在本发明中，当通过第二电介质层形成沟槽时，通过检测第二散装组合物和第一表面组合物之间的差异来确定端点。

公开(公告)号：US06706577B1

公开(公告)日：2004-03-16

申请号：US09298879

申请日：1999-04-26

申请人： Jih-Churng Twu ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Jih-Churng Twu ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L218238

CPC分类号： H01L21/823857 ,  H01L27/10894

摘要： A method of simultaneously forming differential gate oxide for both high and low voltage transistors using a two-step wet oxidation process is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas and wherein there is at least one low voltage area in which a low voltage transistor will be formed and at least one high voltage area in which a high voltage transistor will be formed. The surface of the semiconductor substrate is wet oxidized to form a first layer of gate oxide on the surface of the semiconductor substrate in the active areas. The low voltage active area is covered with a mask. The surface of the semiconductor substrate is wet oxidized again where it is not covered by the mask to form a second layer of gate oxide under the first gate oxide layer in the high voltage active area. The mask is removed. A layer of polysilicon is deposited overlying the first gate oxide layer in the low voltage active area and overlying the second gate oxide layer in the high voltage active area and patterned to form gate electrodes for the low voltage and high voltage transistors in the fabrication of an integrated circuit.

摘要翻译： 描述了使用两步湿氧化工艺同时形成用于高压和低压晶体管的差分栅极氧化物的方法。 提供一种半导体衬底，其中衬底的有源区域与其他有源区域隔离，并且其中存在将形成低压晶体管的至少一个低电压区域和至少一个高电压区域，其中高压晶体管将 形成。 半导体衬底的表面被湿式氧化以在有源区域中在半导体衬底的表面上形成第一层栅极氧化物层。 低电压有源区域用掩模覆盖。 半导体衬底的表面被再次湿式氧化，其中未被掩模覆盖，以在高电压有源区的第一栅氧化层下形成第二层栅氧化层。 去除面具。 一层多晶硅被沉积在低电压有源区中的第一栅极氧化物层上并覆盖在高电压有源区中的第二栅极氧化物层上并被图案化以在制造中形成低电压和高压晶体管的栅电极 集成电路。

公开(公告)号：US06703286B1

公开(公告)日：2004-03-09

申请号：US09354854

申请日：1999-07-29

申请人： Chen-Hua Yu ,  Chung-Shi Liu

发明人： Chen-Hua Yu ,  Chung-Shi Liu

IPC分类号： H01L2176

CPC分类号： H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method is provided whereby successive layers of bond pads can be created. A pattern is created in the preceding level of metal bond pad, a dielectric is deposited over this pattern, openings are created in the dielectric that match the pattern, an opening is created above this pattern and metal is deposited inside this opening creating a square metal bond pad that is joined to the pattern that has been created in the metal of the preceding bond pad.

摘要翻译： 提供了一种可以产生连续的接合层的层的方法。 在金属接合焊盘的先前水平上形成图案，在该图案上沉积电介质，在电介质中形成与图案匹配的开口，在该图案之上形成开口，并且金属沉积在该开口内部，形成方形金属 接合焊盘，其连接到在先前接合焊盘的金属中已经形成的图案。

公开(公告)号：US06686280B1

公开(公告)日：2004-02-03

申请号：US09989802

申请日：2001-11-20

申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

IPC分类号： H01L2100

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

公开(公告)号：US06562725B2

公开(公告)日：2003-05-13

申请号：US09899420

申请日：2001-07-05

申请人： Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Ming-Hsing Tsai ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L2100

CPC分类号： H01L21/76829 ,  H01L21/31116 ,  H01L21/314 ,  H01L21/7681 ,  H01L21/76834

摘要： Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed a first etch stop layer formed of a first material and a second etch stop layer formed of a second material. One of the first material and the second material is a non-nitrogenated silicon carbide material and the other of the first material and the second material is a nitrogenated silicon carbide material. By employing the first material and the second material, there may be etched completely through the first etch stop layer to reach a contact region formed there beneath while not etching completely through the second etch stop layer to reach a first dielectric layer formed there beneath.

摘要翻译： 在用于在微电子制造中形成双镶嵌孔的双镶嵌方法中，采用由第一材料形成的第一蚀刻停止层和由第二材料形成的第二蚀刻停止层。 第一材料和第二材料之一是非氮化碳化硅材料，第一材料和第二材料中的另一种是氮化碳化硅材料。 通过使用第一材料和第二材料，可以完全蚀刻通过第一蚀刻停止层以到达其下方形成的接触区域，而不完全蚀刻通过第二蚀刻停止层，以到达在其下方形成的第一介电层。

公开(公告)号：US06465323B1

公开(公告)日：2002-10-15

申请号：US09898838

申请日：2001-07-03

申请人： Mo-Chiun Yu ,  Shih-Chang Chen ,  Chen-Hua Yu

发明人： Mo-Chiun Yu ,  Shih-Chang Chen ,  Chen-Hua Yu

IPC分类号： H01L2176

CPC分类号： H01L21/823462 ,  H01L21/76224 ,  H01L21/823481

摘要： Within a method for forming a series of gate dielectric layers having a plurality of thicknesses upon a semiconductor substrate, there is sequentially selectively stripped only a series of sacrificial gate dielectric layers only in locations where new gate dielectric layers are desired to be formed, rather masking a only a portion of a partially sacrificial gate dielectric layer which is desired to be retained and stripping a sacrificial remainder of the gate dielectric layer. By employing the sequential selective stripping method, a semiconductor integrated circuit microelectronic fabrication is formed with enhanced reliability insofar as there is attenuated over etching into isolation regions which separate active regions of a semiconductor substrate.

摘要翻译： 在用于在半导体衬底上形成具有多个厚度的一系列栅极电介质层的方法中，仅在期望形成新的栅极电介质层的位置处依次选择性地剥离一系列牺牲栅极介电层，而不是掩蔽 部分牺牲栅极电介质层的仅一部分，其期望被保留并剥离栅极电介质层的牺牲剩余部分。 通过使用顺序选择性剥离方法，半导体集成电路微电子制造形成为具有增强的可靠性，只要在分离半导体衬底的有源区域的隔离区域中进行过蚀刻即可。

公开(公告)号：US06297158B1

公开(公告)日：2001-10-02

申请号：US09583402

申请日：2000-05-31

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC分类号： H01L214763

CPC分类号： H01L21/76873 ,  H01L21/76843 ,  H01L21/76864

摘要： In the presently disclosed invention, a method is provided to avoid damage to a copper interconnect while subjecting the interconnect to chemical-mechanical polishing (CMP). First, a copper barrier layer is formed in a damascene structure. Then, prior to the deposition of copper metal into the damascene openings, a barrier layer is formed on the inside walls of the damascene structure. In a first embodiment, the copper barrier layer is deposited at high temperature. Then, it is cooled down in a prescribed manner. Subsequently, a copper seed layer is formed over the barrier, which is followed by the electro-chemical deposition (ECD) of copper, to form the copper damascene interconnect. Alternatively, in a second embodiment, the copper layer is formed at low temperature. Then it is annealed at a high temperature, followed by wafer cooling. Subsequently, copper seed layer is formed over the barrier layer. Next, ECD copper is formed in the damascene structure. Finally, the interconnect so formed by either of the embodiments is subjected to CMP. It is found that, through the disclosed method of treatment of the barrier layer, process stresses that are normally formed within the barrier layer are relieved, and hence no damage is incurred during the final steps of chemical-mechanical polishing.

摘要翻译： 在本公开的发明中，提供了一种方法，以避免对互连线进行化学机械抛光（CMP）的铜互连的损坏。 首先，在大马士革结构中形成铜阻挡层。 然后，在将铜金属沉积到镶嵌开口之前，在镶嵌结构的内壁上形成阻挡层。 在第一实施例中，铜阻挡层在高温下沉积。 然后，以规定的方式冷却。 随后，在屏障上形成铜籽晶层，随后是铜的电化学沉积（ECD），以形成铜镶嵌互连。 或者，在第二实施例中，铜层在低温下形成。 然后在高温下进行退火，然后进行晶片冷却。 随后，在阻挡层上形成铜籽晶层。 接下来，在镶嵌结构中形成ECD铜。 最后，将由这两个实施例形成的互连件进行CMP处理。 发现通过公开的阻挡层处理方法，通常在阻挡层内形成的工艺应力被释放，因此在化学机械抛光的最终步骤期间不会产生损伤。