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    FinFET with crystalline insulator
    141.
    发明授权
    FinFET with crystalline insulator 有权
    FinFET结晶绝缘体

    公开(公告)号：US09257536B2

    公开(公告)日：2016-02-09

    申请号：US13867247

    申请日：2013-04-22

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

    IPC: H01L29/66

    CPC classification number: H01L29/66795

    Abstract: FinFET structures and methods of formation are disclosed. Fins are formed on a bulk substrate. A crystalline insulator layer is formed on the bulk substrate with the fins sticking out of the epitaxial oxide layer. A gate is formed around the fins protruding from the crystalline insulator layer. An epitaxially grown semiconductor region is formed in the source drain region by merging the fins on the crystalline insulator layer to form a fin merging region.

    Abstract translation: 公开了FinFET结构和形成方法。 翅片形成在块状基底上。 在散装衬底上形成结晶绝缘体层，翅片从外延氧化物层伸出。 在从结晶绝缘体层突出的翅片周围形成栅极。 通过将结晶绝缘体层上的翅片合并形成翅片合并区域，在源漏区域中形成外延生长的半导体区域。

    FINFET structures with fins recessed beneath the gate
    143.
    发明授权
    FINFET structures with fins recessed beneath the gate 有权
    FINFET结构，翅片凹陷在门下

    公开(公告)号：US09246003B2

    公开(公告)日：2016-01-26

    申请号：US14083517

    申请日：2013-11-19

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Kangguo Cheng ,  Eric C. Harley ,  Yue Ke ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC: H01L29/772 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7842 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

    Abstract: A semiconductor structure may include a semiconductor fin, a gate over the semiconductor fin, a spacer on a sidewall of the gate, an angled recess region in an end of the semiconductor fin beneath the spacer, and a first semiconductor region filling the angled recess. The angled recess may be v-shaped or sigma shaped. The structure may further include a second semiconductor region in contact with the first semiconductor region and the substrate. The structure may be formed by forming a gate above a portion of the semiconductor fin on a substrate, forming a spacer on a sidewall of the gate; removing a portion of the semiconductor fin not covered by the spacer or the gate to expose a sidewall of the fin, etching the sidewall of the fin to form an angled recess region beneath the spacer, and filling the angled recess region with a first epitaxial semiconductor region.

    Abstract translation: 半导体结构可以包括半导体鳍片，半导体鳍片上的栅极，栅极的侧壁上的间隔物，在间隔物下方的半导体鳍片的端部中的成角度的凹陷区域以及填充成角度的凹部的第一半导体区域。 成角度的凹槽可以是v形或西格玛形。 该结构还可以包括与第一半导体区域和衬底接触的第二半导体区域。 该结构可以通过在衬底上形成半导体翅片的一部分上方的栅极形成，在栅极的侧壁上形成间隔物; 除去未被间隔物或栅极覆盖的半导体鳍片的一部分以暴露翅片的侧壁，蚀刻翅片的侧壁以在间隔物下方形成倾斜的凹陷区域，并用第一外延半导体填充成角度的凹陷区域 地区。

    Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures
    144.
    发明授权
    Semiconductor devices having fin structures, and methods of forming semiconductor devices having fin structures 有权
    具有翅片结构的半导体器件，以及形成具有翅片结构的半导体器件的方法

    公开(公告)号：US09219139B2

    公开(公告)日：2015-12-22

    申请号：US14081320

    申请日：2013-11-15

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/20

    CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/20 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: A semiconductor device including at least two fin structures on a substrate surface and a functional gate structure present on the at least two fin structures. The functional gate structure includes at least one gate dielectric that is in direct contact with at least the sidewalls of the two fin structures, and at least one gate conductor on the at least one gate dielectric. The sidewall of the gate structure is substantially perpendicular to the upper surface of the substrate surface, wherein the plane defined by the sidewall of the gate structure and a plane defined by an upper surface of the substrate surface intersect at an angle of 90°+/−5°. An epitaxial semiconductor material is in direct contact with the at least two fin structures.

    Abstract translation: 一种半导体器件，包括在衬底表面上的至少两个鳍结构和存在于所述至少两个鳍结构上的功能栅结构。 功能栅极结构包括至少一个与至少两个鳍结构的侧壁直接接触的栅极电介质，以及至少一个栅极电介质上的至少一个栅极导体。 栅极结构的侧壁基本上垂直于衬底表面的上表面，其中由栅极结构的侧壁限定的平面和由衬底表面的上表面限定的平面以90°±/ -5°。 外延半导体材料与至少两个翅片结构直接接触。

    Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs)
    146.
    发明授权
    Structure and method to modulate threshold voltage for high-K metal gate field effect transistors (FETs) 有权
    用于调制高K金属栅场效应晶体管（FET）的阈值电压的结构和方法

    公开(公告)号：US09214397B2

    公开(公告)日：2015-12-15

    申请号：US13788689

    申请日：2013-03-07

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Bruce B. Doris ,  Kangguo Cheng ,  Steven J. Holmes ,  Ali Khakifirooz ,  Pranita Kerber ,  Shom Ponoth ,  Raghavasimhan Sreenivasan ,  Stefan Schmitz

    IPC: H01L21/8238

    CPC classification number: H01L21/823835 ,  H01L21/823842

    Abstract: A method for forming an electrical device that includes forming a high-k gate dielectric layer over a semiconductor substrate that is patterned to separate a first portion of the high-k gate dielectric layer that is present on a first conductivity device region from a second portion of the high-k gate dielectric layer that is present on a second conductivity device region. A connecting gate conductor is formed on the first portion and the second portion of the high-k gate dielectric layer. The connecting gate conductor extends from the first conductivity device region over the isolation region to the second conductivity device region. One of the first conductivity device region and the second conductivity device region may then be exposed to an oxygen containing atmosphere. Exposure with the oxygen containing atmosphere modifies a threshold voltage of the semiconductor device that is exposed.

    Abstract translation: 一种用于形成电气装置的方法，包括在半导体衬底上形成高k栅介质层，该半导体衬底被图案化以将存在于第一导电器件区域上的高k栅介质层的第一部分与第二部分分离 存在于第二导电装置区域上的高k栅介质层。 连接栅极导体形成在高k栅介质层的第一部分和第二部分上。 连接栅极导体从隔离区域上的第一导电器件区域延伸到第二导电器件区域。 然后可以将第一导电器件区域和第二导电器件区域中的一个暴露于含氧气氛中。 用含氧气氛曝光改变暴露的半导体器件的阈值电压。

    Methods of forming isolation material on FinFET semiconductor devices and the resulting devices
    147.
    发明授权
    Methods of forming isolation material on FinFET semiconductor devices and the resulting devices 有权
    在FinFET半导体器件和所得器件上形成隔离材料的方法

    公开(公告)号：US09064890B1

    公开(公告)日：2015-06-23

    申请号：US14223545

    申请日：2014-03-24

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC: H01L29/66 ,  H01L21/8238

    CPC classification number: H01L29/66545 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/785

    Abstract: One method disclosed includes, among other things, forming an initial fin, covering a top surface and a portion of the sidewalls of the initial fin structure with etch stop material, forming a sacrificial gate structure above and around the initial fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one process operation to remove the sacrificial gate structure and thereby define a replacement gate cavity, performing at least one etching process through the replacement gate cavity to remove a portion of the initial fin structure so as to thereby define a final fin structure and a channel cavity positioned below the final fin structure, and substantially filling the channel cavity with an insulating material.

    Abstract translation: 公开的一种方法包括形成初始翅片，用蚀刻停止材料覆盖初始翅片结构的顶表面和一部分侧壁，在初始翅片结构的上方和周围形成牺牲栅结构，形成侧壁 邻近牺牲栅极结构的间隔件，执行至少一个处理操作以去除牺牲栅极结构，从而限定替换栅极腔，通过替代栅极腔执行至少一个蚀刻工艺以去除初始鳍结构的一部分，从而 从而限定最终翅片结构和位于最终翅片结构下方的通道腔，并且用绝缘材料基本上填充通道腔。

    FINFET SEMICONDUCTOR DEVICE WITH A RECESSED LINER THAT DEFINES A FIN HEIGHT OF THE FINFET DEVICE
    150.
    发明申请
    FINFET SEMICONDUCTOR DEVICE WITH A RECESSED LINER THAT DEFINES A FIN HEIGHT OF THE FINFET DEVICE 有权
    FINFET半导体器件，具有限定FINFET器件的高度的衬垫

    公开(公告)号：US20140327088A1

    公开(公告)日：2014-11-06

    申请号：US14333135

    申请日：2014-07-16

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC: H01L29/78

    CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/785

    Abstract: One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin.

    Abstract translation: 本文公开的一种方法包括在限定翅片的多个沟槽中形成共形衬垫层，在衬垫层上方形成绝缘材料层，暴露衬里层的部分，去除衬里层的部分，从而导致 大体呈U形的衬垫，位于每个沟槽的底部，对绝缘材料层进行至少一个第三蚀刻工艺，其中绝缘材料层的至少一部分位于U形的空腔内 衬垫层，并且在翅片周围形成栅极结构。 本文公开的FinFET器件包括限定翅片的多个沟槽，局部隔离，其包括大致U形的衬垫，其部分地限定腔体中定位的空腔和绝缘材料层，以及定位的门结构 围绕翅膀

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