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    High-Rate Chemical Vapor Etch of Silicon Substrates
    142.
    发明申请
    High-Rate Chemical Vapor Etch of Silicon Substrates 有权
    硅衬底的高速化学气相蚀刻

    公开(公告)号：US20140357082A1

    公开(公告)日：2014-12-04

    申请号：US13906392

    申请日：2013-05-31

    Applicant: International Business Machines Corporation

    Inventor： Stephen W. Bedell ,  Gen P. Lauer ,  Isaac Lauer ,  Joseph S. Newbury

    IPC: H01L21/306 ,  H01L21/308

    CPC classification number: H01L21/3065

    Abstract: Methods of etching a silicon substrate at a high rate using a chemical vapor etching process are provided. A silicon substrate may be etched by heating the silicon substrate in a process chamber and then flowing hydrochloric acid and a germanium-carrying compound into the process chamber. The substrate may be heated to at least 700° C. The hydrochloric acid flow rate may be at least approximately 100 (standard cubic centimeters per minute) sccm. In some embodiments, the hydrochloric acid flow rate may be between approximately 10 slm and approximately 20 standard liters per minute (slm). The germanium-carrying compound flow rate may be at least approximately 50 sccm. In some embodiments, the germanium-carrying compound flow rate may be between approximately 100 sccm and approximately 500 sccm. The etching may extend fully through the silicon substrate.

    Abstract translation: 提供了使用化学气相蚀刻工艺以高速度蚀刻硅衬底的方法。 可以通过在处理室中加热硅衬底然后将盐酸和含锗化合物流入处理室来蚀刻硅衬底。 衬底可以被加热到至少700℃。盐酸流速可以是至少约100（标准立方厘米每分钟）sccm。 在一些实施方案中，盐酸流速可以在约10slm至约20标准升/分钟（slm）之间。 携带锗的化合物流速可以至少为约50sccm。 在一些实施方案中，携带锗的化合物流速可以在约100sccm至约500sccm之间。 蚀刻可以完全延伸穿过硅衬底。

    Non-replacement gate nanomesh field effect transistor with pad regions
    143.
    发明授权
    Non-replacement gate nanomesh field effect transistor with pad regions 有权
    具有焊盘区域的非替代栅极纳米场效应晶体管

    公开(公告)号：US08900959B2

    公开(公告)日：2014-12-02

    申请号：US13796278

    申请日：2013-03-12

    Applicant: International Business Machines Corporation

    Inventor： Josephine B. Chang ,  Paul Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

    IPC: H01L21/336 ,  H01L21/20 ,  H01L29/745 ,  H01L29/76 ,  H01L29/775 ,  H01L29/66

    CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/78696

    Abstract: A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.

    Abstract translation: 提供了一种用于形成纳米场效应晶体管的栅极优先处理方案。 将两个不同的半导体材料的交替堆叠图案化以包括两个焊盘区域和纳米线区域。 对另一半导体材料的半导体材料进行横向蚀刻选择性以形成包括悬浮半导体纳米线的纳米片。 在纳米级上形成栅极电介质，栅极电极和栅极帽电介质的堆叠。 在栅电极周围形成介电隔离件。 采用各向同性蚀刻来去除在图案化交替叠层的横向凹槽中形成的介电材料。 可以采用选择性外延工艺来形成源极区和漏极区。

    Diode Structure and Method for Gate All Around Silicon Nanowire Technologies
    144.
    发明申请
    Diode Structure and Method for Gate All Around Silicon Nanowire Technologies 有权
    硅纳米线技术的二极管结构和方法

    公开(公告)号：US20140217507A1

    公开(公告)日：2014-08-07

    申请号：US13761453

    申请日：2013-02-07

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Josephine B. Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

    IPC: H01L29/66 ,  H01L27/12

    CPC classification number: H01L29/66545 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696 ,  H01L29/861 ,  Y10S977/762 ,  Y10S977/888 ,  Y10S977/938

    Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

    Abstract translation: 一种制造电子装置的方法包括以下步骤。 提供了具有在BOX上的SOI层的SOI晶片。 在SOI层中图案化至少一个第一/第二组纳米线和焊盘。 围绕用作晶体管器件的沟道区的第一组纳米线的每一个的一部分选择性地形成共形栅介质层。 第一金属栅极堆叠形成在共形栅极介电层上，围绕作为晶体管器件的沟道区域的第一组纳米线的每一个的栅极全部构型。 形成第二金属栅极叠层，围绕作为二极管器件的栅极全部配置的沟道区的第二组纳米线的每一个的一部分。

    QUBIT PULSE CALIBRATION VIA CANARY PARAMETER MONITORING
    145.
    发明申请
    QUBIT PULSE CALIBRATION VIA CANARY PARAMETER MONITORING 有权

    公开(公告)号：US20220019927A1

    公开(公告)日：2022-01-20

    申请号：US16929922

    申请日：2020-07-15

    Applicant: International Business Machines Corporation

    Inventor： Isaac Lauer

    IPC: G06N10/00 ,  G06F11/30 ,  G06F11/34

    Abstract: Systems and techniques that facilitate qubit pulse calibration via canary parameter monitoring are provided. In various embodiments, a system can comprise a measurement component that can measure a canary parameter associated with a qubit control channel. In various embodiments, the system can further comprise a scaling component that can modify a plurality of parameters associated with the qubit control channel via a scaling factor. In various cases, the scaling factor can be based on the canary parameter. In various embodiments, the canary parameter can be a rotation error of a qubit driven by a microwave pulse transmitted along the qubit control channel. In various embodiments, the plurality of parameters can be amplitudes of a plurality of microwave pulses transmitted along the qubit control channel. In various embodiments, the plurality of parameters can be phases of a plurality of microwave pulses transmitted along the qubit control channel.

    Gate-to-bulk substrate isolation in gate-all-around devices
    148.
    发明授权
    Gate-to-bulk substrate isolation in gate-all-around devices 有权

    公开(公告)号：US10170636B2

    公开(公告)日：2019-01-01

    申请号：US15603945

    申请日：2017-05-24

    Applicant: International Business Machines Corporation

    Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

    IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311

    Abstract: A method for fabricating a semiconductor device comprises forming a sacrificial layer of a first semiconductor material on a substrate, a layer of a second semiconductor material on the sacrificial layer, and a layer of a third semiconductor material on the layer of the second semiconductor material. Portions of the layer of the deposited material are removed to form a first nanowire arranged on the sacrificial fin and a second nanowire arranged on the first nanowire. An oxidizing process is performed that forms a first layer of oxide material on exposed portions of the second nanowire and a second layer of oxide material on exposed portions of the sacrificial fin, the first layer of oxide material having a first thickness and the second layer of oxide material having a second thickness, where the first thickness is less than the second thickness.

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