公开(公告)号：US20180358074A1

公开(公告)日：2018-12-13

申请号：US15619163

申请日：2017-06-09

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2293

Abstract: Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. In some examples, the duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

公开(公告)号：US20180190337A1

公开(公告)日：2018-07-05

申请号：US15855326

申请日：2017-12-27

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Scott James Derner ,  Umberto Di Vincenzo ,  Christopher John Kawamura ,  Eric S. Carman

IPC: G11C11/22

CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2293

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.

公开(公告)号：US20170352417A1

公开(公告)日：2017-12-07

申请号：US15670920

申请日：2017-08-07

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Simone Lombardo

IPC: G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0038 ,  G11C2211/5645 ,  G11C2213/72

Abstract: Apparatus and methods utilize a replica circuit to generate a voltage for programming of a memory cell, such as a memory cell of a phase-change memory (PCM). Current passing through a circuit including the memory cell to be programmed is mirrored in a scaled or unscaled manner, and provided as an input to the replica circuit. The replica circuit represents voltage drops that should be encountered when programming the memory cell. An input voltage is also provided to the replica circuit, which affects the voltage drop within the replica circuit that represents the voltage drop of the cell. The voltage drop across the replica circuit can then be mirrored and provided to bias the circuit including the memory cell.

公开(公告)号：US12062389B2

公开(公告)日：2024-08-13

申请号：US17323968

申请日：2021-05-18

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C11/22

CPC classification number: G11C11/2259 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2257 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293

Abstract: Methods, systems, and devices for accessing a ferroelectric memory cell are described. In some examples, during a first portion of an access procedure, the voltages of a digit line and word line coupled with the memory cell may be increased while the voltage of a plate coupled with the memory cell is held constant, which may support sensing a logic state stored by the memory cell prior the access procedure, and which may result in a first logic state being written to the memory cell. A voltage of the plate may then be increased, and the digit line may then be coupled with the plate. Because the first logic state was previously written to the memory cell, a target logic state may not need to be subsequently written to the memory cell unless different than the first logic state.

公开(公告)号：US20240249777A1

公开(公告)日：2024-07-25

申请号：US18601810

申请日：2024-03-11

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/26 ,  G11C16/30

Abstract: Apparatuses, methods, and systems for storing one data value by programming a first memory cell and a second memory cell are disclosed. The first memory cell and the second memory cell may each be programmed to a first data state, a second data state, or a third data state, and the one data value can correspond to a combination of the first data state, the second data state, or the third data state to which the first memory cell and the second memory cell are programmed, where two combinations of the first data state, the second data state, or the third data state to which the first memory cell is programmable and the first data state, the second data state, or the third data state to which the second memory cell is programmable are ineligible to correspond to the one data value.

公开(公告)号：US20240212736A1

公开(公告)日：2024-06-27

申请号：US18528451

申请日：2023-12-04

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C11/22 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/2257 ,  G11C11/2273 ,  G11C11/4085 ,  G11C11/4091

Abstract: Methods, systems, and devices for word line charge integration are described. In some examples, a memory device may include a plurality of memory cells that are coupled with a word line and respective digit lines. During a read operation, the word line may be activated (e.g., driven to a voltage) and a subset of the respective digit lines may be activated (e.g., driven to a voltage) to begin integrating charges of each of the memory cells. Before each digit line is activated, the word line may be deactivated and the remaining digit lines may be activated (e.g., driven to a voltage) to begin integrating charges of the remaining memory cells that are coupled with the word line. After each of the digit lines are selected, respective sense components may be activated to sense the charges associated with the memory cells.

公开(公告)号：US20240177792A1

公开(公告)日：2024-05-30

申请号：US18521891

申请日：2023-11-28

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C29/46 ,  G11C29/12 ,  G11C29/42

CPC classification number: G11C29/46 ,  G11C29/1201 ,  G11C29/42

Abstract: Methods, systems, and devices related to counter-based sense amplifier method for memory cells are described. The counter-based read algorithm may comprise the following phases:



storing in a counter associated to an array of memory cells the value of the number of bits having a predetermined logic value of the data bits stored in the memory array;
reading from said counter the value corresponding to the number of bits having the predetermined logic value;
reading the data stored in the array of memory cells by applying a ramp of biasing voltages;
counting the number of bits having the predetermined logic value during the data reading phase;
stopping the data reading phase when the number of bits having the predetermined logic value is equal to the value stored in said counter.

公开(公告)号：US11901029B2

公开(公告)日：2024-02-13

申请号：US18112307

申请日：2023-02-21

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C29/42 ,  G11C29/44 ,  G11C7/14 ,  G11C29/20 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C7/14 ,  G11C29/12005 ,  G11C29/20 ,  G11C29/44

Abstract: Methods and apparatuses with counter-based reading are described. A memory cells of a codeword are accessed and respective voltages are generated. A reference voltage is generated and a logic state of each memory cell is determined based on the reference voltage and the respective generated cell voltage. The reference voltage is modified until a count of memory cells determined to be in a predefined logic state with respect to the last modified reference voltage value meets a criterium. In some embodiments the criterium may be an exact match between the memory cells count and an expected number of memory cells in the predefined logic state. In other embodiments, an error correction (ECC) algorithm may be applied while the difference between the count of cells in the predefined logic state and the expected number of cells in that state does not exceed a detection or correction power of the ECC.

公开(公告)号：US20240038322A1

公开(公告)日：2024-02-01

申请号：US17873991

申请日：2022-07-26

Applicant: Micron Technology, Inc.

Inventor： Michele Maria Venturini ,  Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Christophe Vincent Antoine Laurent ,  Christian Caillat

IPC: G11C29/50

CPC classification number: G11C29/50004 ,  G11C2029/5004

Abstract: Apparatuses, methods, and systems for performing sense operations in memory are disclosed. The memory can have a group of memory cells, and circuitry can be configured to perform a sense operation on the group, wherein performing the sense operation includes performing a first sense operation in a first polarity on the group of memory cells to determine a quantity of the memory cells of the group that are in a particular data state, and performing a second sense operation in a second polarity on the group of memory cells to determine a data state of the memory cells of the group. The second polarity is opposite the first polarity, and the second sense operation is a count-based sense operation that uses the determined quantity of memory cells in the particular data state as a counting threshold to determine the data state of the memory cells of the group.

公开(公告)号：US11881252B2

公开(公告)日：2024-01-23

申请号：US17411721

申请日：2021-08-25

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Lucia Di Martino

IPC: G11C11/22 ,  G11C11/4091 ,  G11C11/4074 ,  G11C7/02

CPC classification number: G11C11/4091 ,  G11C7/02 ,  G11C11/2273 ,  G11C11/4074

Abstract: Techniques are described herein for mitigating parasitic signals induced by state transitions during an access operation of a selected memory cell in a memory device. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended coupling between various components of the memory device may occur during an access operation. To mitigate parasitic signals induced by the unintended coupling, the memory device may isolate the selected memory cell from a selected digit line during certain portions of the access operation. The memory device may isolate the selected memory cell when the plate transitions from a first voltage to a second, when the selected digit line transitions from a third voltage to a fourth voltage, or a combination thereof.