公开(公告)号：US20180301547A1

公开(公告)日：2018-10-18

申请号：US16013095

申请日：2018-06-20

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Salih Muhsin Celik

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L29/51 ,  H01L29/739

CPC classification number: H01L29/66977 ,  H01L29/0649 ,  H01L29/083 ,  H01L29/0834 ,  H01L29/165 ,  H01L29/4941 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/7851

Abstract: A tunneling field effect transistor is formed from a fin of semiconductor material on a support substrate. The fin of semiconductor material includes a source region, a drain region and a channel region between the source region and drain region. A gate electrode straddles over the fin at the channel region. Sidewall spacers are provided on each side of the gate electrode. The source of the transistor is made from an epitaxial germanium content source region grown from the source region of the fin and doped with a first conductivity type. The drain of the transistor is made from an epitaxial silicon content drain region grown from the drain region of the fin and doped with a second conductivity type.

公开(公告)号：US10062762B2

公开(公告)日：2018-08-28

申请号：US14581857

申请日：2014-12-23

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Chun-chen Yeh ,  Ruilong Xie

IPC: H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L23/535 ,  H01L23/538 ,  H01L29/43 ,  H01L29/40 ,  H01L29/49 ,  H01L29/45 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L29/51 ,  H01L23/48

CPC classification number: H01L29/45 ,  H01L21/76816 ,  H01L21/823821 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/535 ,  H01L23/5386 ,  H01L29/401 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: The present disclosure is directed to a device and method for reducing the resistance of the middle of the line in a transistor. The transistor has electrical contacts formed above, and electrically connected to, the gate, drain and source. The electrical contact connected to the gate includes a tungsten contact member deposited over the gate, and a copper contact deposited over the tungsten contact member. The electrical contacts connected to the drain and source include tungsten portions deposited over the drain and source regions, and copper contacts deposited over the tungsten portions.

公开(公告)号：US10043907B2

公开(公告)日：2018-08-07

申请号：US15162441

申请日：2016-05-23

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/762 ,  H01L29/10 ,  H01L29/49 ,  H01L29/165 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L21/225 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161

Abstract: A method for forming a complementary metal oxide semiconductor (CMOS) semiconductor device includes providing a stressed silicon-on-insulator (sSOI) wafer comprising a stressed semiconductor layer having first and second laterally adjacent stressed semiconductor portions. The first stressed semiconductor portion defines a first active region. The second stressed semiconductor portion is replaced with an unstressed semiconductor portion. The unstressed semiconductor portion includes a first semiconductor material. The method further includes driving a second semiconductor material into the first semiconductor material of the unstressed semiconductor portion defining a second active region.

公开(公告)号：US10038075B2

公开(公告)日：2018-07-31

申请号：US15437487

申请日：2017-02-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Stephane Allegret-Maret ,  Kangguo Cheng ,  Bruce Doris ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/11

CPC classification number: H01L29/66772 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/78654

Abstract: An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region.

公开(公告)号：US20180158739A1

公开(公告)日：2018-06-07

申请号：US15890001

申请日：2018-02-06

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/423 ,  H01L29/161 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L27/12 ,  H01L27/02 ,  H01L21/308 ,  H01L21/266

CPC classification number: H01L21/845 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3081 ,  H01L27/0207 ,  H01L27/1211 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/4236 ,  H01L29/66795

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

公开(公告)号：US20180102395A1

公开(公告)日：2018-04-12

申请号：US15829397

申请日：2017-12-01

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528

CPC classification number: H01L27/2436 ,  H01L23/528 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1691

Abstract: A memory cell includes a substrate layer, with a plurality of silicided semiconductor fins stacked on the substrate layer and spaced apart from one another. A first metal liner layer is stacked on the plurality of silicided semiconductor fins and on the substrate layer. A plurality of first contact pillars are stacked on the first metal liner layer adjacent a different respective one of the plurality of silicided semiconductor fins. A configurable resistance structure covers portions of the first metal liner layer that are stacked on the substrate layer and portions of the first metal liner layer that are stacked on each of the plurality of silicided semiconductor fins. A metal fill layer is stacked on the configurable resistance structure. A plurality of second contact pillars is stacked on the metal fill layer adjacent a space between a different pair of adjacent silicided semiconductor fins of the plurality thereof.

公开(公告)号：US20180096883A1

公开(公告)日：2018-04-05

申请号：US15831761

申请日：2017-12-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Bruce Doris ,  Hong He ,  Qing Liu

IPC: H01L21/762 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02 ,  H01L29/06 ,  H01L27/12 ,  H01L21/225

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.

公开(公告)号：US09917020B2

公开(公告)日：2018-03-13

申请号：US15238559

申请日：2016-08-16

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L27/12 ,  H01L27/02 ,  H01L21/84 ,  H01L21/266 ,  H01L21/265 ,  H01L21/308 ,  H01L29/06 ,  H01L29/10 ,  H01L29/161 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3081 ,  H01L27/0207 ,  H01L27/1211 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/4236 ,  H01L29/66795

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

公开(公告)号：US09793395B1

公开(公告)日：2017-10-17

申请号：US15287134

申请日：2016-10-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-chen Yeh

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L29/417

CPC classification number: H01L29/7827 ,  H01L21/02614 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/41741 ,  H01L29/66553 ,  H01L29/66666

Abstract: A method of fabricating features of a vertical transistor include performing a first etch process to form a first portion of a fin in a substrate; depositing a spacer material on sidewalls of the first portion of the fin; performing a second etch process using the spacer material as a pattern to elongate the fin and form a second portion of the fin in the substrate, the second portion having a width that is greater than the first portion; oxidizing a region of the second portion of the fin beneath the spacer material to form an oxidized channel region; and removing the oxidized channel region to form a vacuum channel.

公开(公告)号：US09755031B2

公开(公告)日：2017-09-05

申请号：US14577431

申请日：2014-12-19

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

Inventor： Qing Liu ,  Xiuyu Cai ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/41783 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A FinFET device includes a semiconductor fin, a gate electrode extending over a channel of the fin and sidewall spacers on each side of the gate electrode. A dielectric material is positioned on each side of a bottom portion of said fin, with an oxide material on each side of the fin overlying the dielectric material. A recessed region, formed in the fin on each side of the channel region, is delimited by the oxide material. A raised source region fills the recessed region and extends from the fin on a first side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer. A raised drain region fills the recessed region and extends from the fin on a second side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer.