公开(公告)号：US20120145799A1

公开(公告)日：2012-06-14

申请号：US13372877

申请日：2012-02-14

申请人： Jun KOYAMA ,  Shunpei YAMAZAKI

发明人： Jun KOYAMA ,  Shunpei YAMAZAKI

IPC分类号： G06K19/077

CPC分类号： G06K19/0723 ,  G06K19/0719

摘要： A semiconductor device with improved reliability, in which increase in power consumption can be reduced. The semiconductor device includes an antenna for transmitting and receiving a wireless signal to/from a communication device and at least first and second functional circuits electrically connected to the antenna. The first functional circuit includes a power supply control circuit for controlling power supply voltage output from a power supply circuit in the second functional circuit. A power supply control circuit in the second functional circuit includes a transistor of which first terminal is electrically connected to an output terminal of the power supply circuit and second terminal is electrically connected to a ground line. A gate terminal of the transistor is electrically connected to the power supply control circuit included in one functional circuit.

摘要翻译： 具有可靠性提高的能够降低功耗增加的半导体装置。 半导体器件包括用于向/从通信设备发送和接收无线信号的天线以及电连接到天线的至少第一和第二功能电路。 第一功能电路包括用于控制从第二功能电路中的电源电路输出的电源电压的电源控制电路。 第二功能电路中的电源控制电路包括晶体管，其第一端子电连接到电源电路的输出端子，并且第二端子电连接到接地线。 晶体管的栅极端子电连接到包括在一个功能电路中的电源控制电路。

公开(公告)号：US20120122277A1

公开(公告)日：2012-05-17

申请号：US13356044

申请日：2012-01-23

申请人： Shunpei YAMAZAKI ,  Kengo AKIMOTO

发明人： Shunpei YAMAZAKI ,  Kengo AKIMOTO

IPC分类号： H01L21/34

CPC分类号： H01L29/78696 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/02565 ,  H01L29/247 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693

摘要： An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such as moisture. Another object is to provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability, and a method by which a semiconductor device can be manufactured with high productivity. A main point is to perform oxygen radical treatment on a surface of a gate insulating layer. Accordingly, there is a peak of the oxygen concentration at an interface between the gate insulating layer and a semiconductor layer, and the oxygen concentration of the gate insulating layer has a concentration gradient. The oxygen concentration is increased toward the interface between the gate insulating layer and the semiconductor layer.

摘要翻译： 本发明的目的是提供一种薄膜晶体管的有利的界面特性，该薄膜晶体管包括氧化物半导体层，而不混入杂质如水分。 另一个目的是提供一种包括具有优异的电特性和高可靠性的薄膜晶体管的半导体器件，以及可以以高生产率制造半导体器件的方法。 要点是在栅极绝缘层的表面进行氧自由基处理。 因此，在栅极绝缘层与半导体层之间的界面处存在氧浓度的峰值，并且栅极绝缘层的氧浓度具有浓度梯度。 氧浓度朝向栅极绝缘层和半导体层之间的界面增加。

公开(公告)号：US20120119252A1

公开(公告)日：2012-05-17

申请号：US13294458

申请日：2011-11-11

申请人： Kaoru KATO ,  Shunpei YAMAZAKI

发明人： Kaoru KATO ,  Shunpei YAMAZAKI

IPC分类号： H01L33/62

CPC分类号： H01L51/5048

摘要： It is an object of the present invention to provide a light emitting element with low drive voltage. In addition, it is another object to provide a light emitting device having the light emitting element. Further in addition, it is another object to provide an electric appliance which has a light emitting element with low drive voltage. A light emitting element of the present invention comprises a pair of electrodes, a layer containing a light emitting element and a layer containing a mixture material which contains a conductive material formed from an inorganic compound and an insulating material formed from an inorganic compound, which are interposed between the pair of electrodes, wherein the layer containing the mixture material has a resistivity of 50,000 to 1,000,000 ohm cm, preferably, 200,000 to 500,000 ohm cm. The drive voltage of the light emitting element can be lowered with the foregoing structure.

摘要翻译： 本发明的目的是提供一种具有低驱动电压的发光元件。 另外，另一个目的是提供一种具有发光元件的发光器件。 此外，另一目的是提供一种具有低驱动电压的发光元件的电器。 本发明的发光元件包括一对电极，包含发光元件的层和含有由无机化合物形成的导电材料和由无机化合物形成的绝缘材料的混合材料的层，它们是 插入在该对电极之间，其中含有混合材料的层的电阻率为50,000至1,000,000欧姆厘米，优选为20万至50万欧姆厘米。 通过上述结构，能够降低发光元件的驱动电压。

公开(公告)号：US20120108006A1

公开(公告)日：2012-05-03

申请号：US13346118

申请日：2012-01-09

申请人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

发明人： Shunpei YAMAZAKI ,  Hidekazu MIYAIRI ,  Kengo AKIMOTO ,  Kojiro SHIRAISHI

IPC分类号： H01L21/36

CPC分类号： H01L29/66969 ,  H01L21/46 ,  H01L27/1225 ,  H01L29/7869

摘要： It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

公开(公告)号：US20120104568A1

公开(公告)日：2012-05-03

申请号：US13348097

申请日：2012-01-11

申请人： Shunpei YAMAZAKI

发明人： Shunpei YAMAZAKI

IPC分类号： H01L23/00

CPC分类号： H01L27/1266 ,  H01L27/1214 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a method for manufacturing a large-area semiconductor device, to provide a method for manufacturing a semiconductor device with high efficiency, and to provide a highly-reliable semiconductor device in the case of using a large-area substrate including an impurity element. A plurality of single crystal semiconductor substrates are concurrently processed to manufacture an SOI substrate, so that an area of a semiconductor device can be increased and a semiconductor device can be manufactured with improved efficiency. In specific, a series of processes is performed using a tray with which a plurality of semiconductor substrates can be concurrently processed. Here, the tray is provided with at least one depression for holding single crystal semiconductor substrates. Further, deterioration of characteristics of a manufactured semiconductor element is prevented by providing an insulating layer serving as a barrier layer against an impurity element which may affect characteristics of the semiconductor element.

摘要翻译： 为了提供一种制造大面积半导体器件的方法，提供一种高效率制造半导体器件的方法，并且在使用包括杂质元素的大面积衬底的情况下提供高可靠性的半导体器件。 同时处理多个单晶半导体衬底以制造SOI衬底，使得可以增加半导体器件的面积并且可以以更高的效率制造半导体器件。 具体而言，使用能够同时处理多个半导体基板的托盘进行一系列处理。 这里，托盘设置有用于保持单晶半导体衬底的至少一个凹部。 此外，通过为可能影响半导体元件的特性的杂质元素提供用作阻挡层的绝缘层来防止制造的半导体元件的特性劣化。

公开(公告)号：US20120099048A1

公开(公告)日：2012-04-26

申请号：US13277417

申请日：2011-10-20

申请人： Shunpei YAMAZAKI ,  Yoshiharu Hirakata

发明人： Shunpei YAMAZAKI ,  Yoshiharu Hirakata

IPC分类号： G02F1/1335 ,  H01L33/58 ,  H01L33/08 ,  H01L33/50

CPC分类号： H01L33/505 ,  G02F1/133514 ,  G02F1/133603 ,  G02F1/133621 ,  H01L25/0753 ,  H01L33/465 ,  H01L33/486 ,  H01L33/50 ,  H01L33/54 ,  H01L33/56 ,  H01L33/62 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2924/07811 ,  H01L2924/1461 ,  H01L2924/3025 ,  H01L2924/00

摘要： A light-emitting element unit which can improve color purity of light emitted from a color filter is provided. A display device with high color purity and high color reproducibility is provided. The light-emitting element unit includes a wiring board, a light-emitting element chip provided over the wiring board, a micro optical resonator provided over the wiring board and at the periphery of the light-emitting element chip, and a phosphor layer covering the light-emitting element chip and the micro optical resonator. The display device includes a display panel having a coloring layer and a backlight module having the light-emitting element unit. Examples of the display panel include: a liquid crystal panel; and a display panel including an opening portion provided over a first substrate, MEMS moving over the opening portion in the lateral direction, and a second substrate provided with a coloring layer in a portion corresponding to the opening portion.

摘要翻译： 提供了可以提高从滤色器发出的光的色纯度的发光元件单元。 提供了具有高纯度和高色彩再现性的显示装置。 发光元件单元包括布线板，设置在布线板上的发光元件芯片，设置在布线板上和发光元件芯片周围的微光谐振器，以及覆盖该发光元件芯片的荧光体层 发光元件芯片和微光谐振器。 显示装置包括具有着色层的显示面板和具有发光元件单元的背光模块。 显示面板的实例包括：液晶面板; 以及显示面板，包括设置在第一基板上的开口部分，在横向方向上在开口部分上移动的MEMS以及在与开口部分相对应的部分中设置有着色层的第二基板。

公开(公告)号：US20120074418A1

公开(公告)日：2012-03-29

申请号：US13298469

申请日：2011-11-17

申请人： Shunpei YAMAZAKI

发明人： Shunpei YAMAZAKI

IPC分类号： H01L27/12

CPC分类号： H01L27/124 ,  H01L27/1214 ,  H01L27/127 ,  H01L29/42384 ,  H01L2029/7863

摘要： NTFT of the present invention has a channel forming region, n-type first, second, and third impurity regions in a semiconductor layer. The second impurity region is a low concentration impurity region that overlaps a tapered potion of a gate electrode with a gate insulating film interposed therebetween, and the impurity concentration of the second impurity region increases gradually from the channel forming region to the first impurity region. And, the third impurity region is a low concentration impurity region that does not overlap the gate electrode. Moreover, a plurality of NTFTs on the same substrate have different second impurity region lengths, respectively, according to difference of the operating voltages. That is, when the operating voltage of the second TFT is higher than the operating voltage of the first TFT, the length of the second impurity region is longer on the second TFT than on the first TFT.

摘要翻译： 本发明的NTFT在半导体层中具有沟道形成区域，n型第一，第二和第三杂质区域。 第二杂质区域是与栅电极的锥形部分重叠的低浓度杂质区域，其间插入有栅极绝缘膜，并且第二杂质区域的杂质浓度从沟道形成区域逐渐增加到第一杂质区域。 并且，第三杂质区域是不与栅电极重叠的低浓度杂质区域。 此外，根据工作电压的差异，同一衬底上的多个NTFT分别具有不同的第二杂质区长度。 也就是说，当第二TFT的工作电压高于第一TFT的工作电压时，第二TFT上的第二杂质区域的长度比第一TFT长。

公开(公告)号：US20120074407A1

公开(公告)日：2012-03-29

申请号：US13021343

申请日：2011-02-04

申请人： Shunpei YAMAZAKI ,  Teruyuki FUJII ,  Ryota IMAHAYASHI ,  Shinya SASAGAWA ,  Motomu KURATA ,  Fumika TAGUCHI

发明人： Shunpei YAMAZAKI ,  Teruyuki FUJII ,  Ryota IMAHAYASHI ,  Shinya SASAGAWA ,  Motomu KURATA ,  Fumika TAGUCHI

IPC分类号： H01L27/06 ,  H01L21/336

CPC分类号： H01L27/0688 ,  G11C16/0416 ,  G11C16/0433 ,  G11C16/28 ,  H01L27/1052 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225

摘要： An object is to provide a semiconductor device having a novel structure in which a transistor including an oxide semiconductor and a transistor including a semiconductor material other than an oxide semiconductor are stacked. The semiconductor device includes a first transistor, an insulating layer over the first transistor, and a second transistor over the insulating layer. In the semiconductor device, the first transistor includes a first channel formation region, the second transistor includes a second channel formation region, the first channel formation region includes a semiconductor material different from a semiconductor material of the second channel formation region, and the insulating layer includes a surface whose root-mean-square surface roughness is less than or equal to 1 nm.

摘要翻译： 目的是提供一种具有新颖结构的半导体器件，其中包括氧化物半导体的晶体管和包括氧化物半导体之外的半导体材料的晶体管被​​堆叠。 该半导体器件包括第一晶体管，第一晶体管上的绝缘层和绝缘层上的第二晶体管。 在半导体器件中，第一晶体管包括第一沟道形成区，第二晶体管包括第二沟道形成区，第一沟道形成区包括与第二沟道形成区的半导体材料不同的半导体材料，绝缘层 包括均方根表面粗糙度小于或等于1nm的表面。

公开(公告)号：US20120064677A1

公开(公告)日：2012-03-15

申请号：US13225703

申请日：2011-09-06

申请人： Hidekazu MIYAIRI ,  Koji DAIRIKI ,  Shunpei YAMAZAKI ,  Ryo ARASAWA

发明人： Hidekazu MIYAIRI ,  Koji DAIRIKI ,  Shunpei YAMAZAKI ,  Ryo ARASAWA

IPC分类号： H01L21/336

CPC分类号： H01L29/78678 ,  H01L29/66765 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/78669 ,  H01L29/78696

摘要： Provided is a method for manufacturing a semiconductor device with fewer masks and in a simple process. A gate electrode is formed. A gate insulating film, a semiconductor film, an impurity semiconductor film, and a conductive film are stacked in this order, covering the gate electrode. A source electrode and a drain electrode are formed by processing the conductive film. A source region, a drain region, and a semiconductor layer, an upper part of a portion of which does not overlap with the source region and the drain region is removed, are formed by processing the upper part of the semiconductor film, while the impurity semiconductor film is divided. A passivation film over the gate insulating film, the semiconductor layer, the source region, the drain region, the source electrode, and the drain electrode are formed. An etching mask is formed over the passivation film. At least the passivation film and the semiconductor layer are processed to have an island shape while an opening reaching the source electrode or the drain electrode is formed, with the use of the etching mask. The etching mask is removed. A pixel electrode is formed over the gate insulating film and the passivation film.

摘要翻译： 提供一种用于制造具有较少掩模的半导体器件的方法，并且在简单的过程中。 形成栅电极。 依次层叠栅绝缘膜，半导体膜，杂质半导体膜和导电膜，覆盖栅电极。 通过处理导电膜形成源电极和漏电极。 通过处理半导体膜的上部，形成源区域，漏极区域和半导体层，其部分的上部不与源极区域和漏极区域重叠，而杂质 半导体薄膜被划分。 形成栅极绝缘膜，半导体层，源极区域，漏极区域，源极电极和漏极电极之后的钝化膜。 在钝化膜上形成蚀刻掩模。 通过使用蚀刻掩模，至少钝化膜和半导体层被加工成具有岛状，同时形成到达源电极或漏电极的开口。 去除蚀刻掩模。 在栅极绝缘膜和钝化膜上形成像素电极。

公开(公告)号：US20120062809A1

公开(公告)日：2012-03-15

申请号：US13233120

申请日：2011-09-15

申请人： Chiho KOKUBO ,  Hirokazu YAMAGATA ,  Shunpei YAMAZAKI

发明人： Chiho KOKUBO ,  Hirokazu YAMAGATA ,  Shunpei YAMAZAKI

IPC分类号： G02F1/133

CPC分类号： H01L21/02672 ,  G02F1/13454 ,  G09G3/30 ,  G09G3/3225 ,  G09G3/3233 ,  G09G3/3648 ,  G09G2300/0842 ,  G09G2300/0861 ,  H01L21/02532 ,  H01L21/2022 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1277 ,  H01L27/3244 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78624 ,  H01L29/78645 ,  H01L29/78675

摘要： There is disclosed a semiconductor device and a method of fabricating the semiconductor device in which a heat treatment time required for crystal growth is shortened and a process is simplified. Two catalytic element introduction regions are arranged at both sides of one active layer and crystallization is made. A boundary portion where crystal growth from one catalytic element introduction region meets crystal growth from the other catalytic element introduction region is formed in a region which becomes a source region or drain region.

摘要翻译： 公开了半导体器件和制造半导体器件的方法，其中缩短了晶体生长所需的热处理时间并简化了工艺。 两个催化元素引入区域布置在一个有源层的两侧，并进行结晶。 在成为源极区域或漏极区域的区域中形成有来自一个催化剂元件导入区域的晶体生长与其他催化剂元素导入区域的晶体生长相交的边界部分。