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    Memory systems and methods for improved power management
    151.
    发明授权
    Memory systems and methods for improved power management 有权

    公开(公告)号：US12300307B2

    公开(公告)日：2025-05-13

    申请号：US18203591

    申请日：2023-05-30

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  James E. Harris

    IPC: G11C5/04 ,  G11C5/06 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4093

    Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. Each memory device supports an access mode and a low-power mode, the latter used to save power for devices that are not immediately needed. The module provides granular power management using a chip-select decoder that decodes chip-select signals from the memory controller into power-state signals that determine which of the memory devices are in which of the modes. Devices can thus be brought out of the low-power mode in relatively small numbers, as needed, to limit power consumption.

    Memory device and repair method with column-based error code tracking
    152.
    发明授权
    Memory device and repair method with column-based error code tracking 有权

    公开(公告)号：US12287705B2

    公开(公告)日：2025-04-29

    申请号：US18444320

    申请日：2024-02-16

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent Steven Haukness

    IPC: G06F11/10 ,  G06F12/02 ,  G11C29/52

    Abstract: A memory device is disclosed that includes a row of storage locations that form plural columns. The plural columns include data columns to store data and a tag column to store tag information associated with error locations in the data columns. Each data column is associated with an error correction location including an error code bit location. Logic retrieves and stores the tag information associated with the row in response to activation of the row. A bit error in an accessed data column is repaired by a spare bit location based on the tag information.

    MEMORY COMPONENT WITH ADJUSTABLE CORE-TO-INTERFACE DATA RATE RATIO
    154.
    发明申请
    MEMORY COMPONENT WITH ADJUSTABLE CORE-TO-INTERFACE DATA RATE RATIO 有权

    公开(公告)号：US20250054525A1

    公开(公告)日：2025-02-13

    申请号：US18809247

    申请日：2024-08-19

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely K. Tsern

    IPC: G11C7/10

    Abstract: A memory component includes a memory bank comprising a plurality of storage cells and a data interface block configured to transfer data between the memory component and a component external to the memory component. The memory component further includes a plurality of column interface buses coupled between the memory bank and the data interface block, wherein a first column interface bus of the plurality of column interface buses is configured to transfer data between a first storage cell of the plurality of storage cells and the data interface block during a first access operation and wherein a second column interface bus of the plurality of column interface buses is configured to transfer the data between the first storage cell and the data interface block during a second access operation.

    Protocol for refresh between a memory controller and a memory device
    156.
    发明授权
    Protocol for refresh between a memory controller and a memory device 有权

    公开(公告)号：US12211540B2

    公开(公告)日：2025-01-28

    申请号：US18399096

    申请日：2023-12-28

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent Haukness

    IPC: G06F12/00 ,  G06F13/16 ,  G11C11/406

    Abstract: The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device, to a self-refresh state, wherein the memory device controls the refreshing operations. While the memory device is in the self-refresh state, the system sends progress information for the refreshing operations from the memory device to the memory controller. Next, upon returning from the self-refresh state to the auto-refresh state, the system uses the progress information received from the memory device to control the sequencing of subsequent operations by the memory controller.

    Memory system with threaded transaction support
    157.
    发明授权
    Memory system with threaded transaction support 有权

    公开(公告)号：US12197731B2

    公开(公告)日：2025-01-14

    申请号：US18492296

    申请日：2023-10-23

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely Tsern

    IPC: G06F3/06 ,  G06F12/06 ,  G11C5/04 ,  G11C7/10

    Abstract: Memory modules, systems, memory controllers and associated methods are disclosed. In one embodiment, a memory module includes a module substrate having first and second memory devices. Buffer circuitry disposed on the substrate couples to the first and second memory devices via respective first and second secondary interfaces. The buffer circuitry includes a primary signaling interface for coupling to a group of signaling links associated with a memory controller. The primary signaling interface operates at a primary signaling rate and the first and second secondary data interfaces operate at a secondary signaling rate. During a first mode of operation, the primary interface signaling rate is at least twice the secondary signaling rate. A first time interval associated with a transfer of first column data via the first secondary interface temporally overlaps a second time interval involving second column data transferred via the second secondary interface.

    Nonvolatile physical memory with DRAM cache
    158.
    发明授权
    Nonvolatile physical memory with DRAM cache 有权

    公开(公告)号：US12135645B2

    公开(公告)日：2024-11-05

    申请号：US18203569

    申请日：2023-05-30

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Christopher Haywood

    IPC: G06F12/0804 ,  G06F12/12 ,  G11C14/00

    Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

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