公开(公告)号：US10014379B2

公开(公告)日：2018-07-03

申请号：US14526980

申请日：2014-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai

IPC: H01L21/8238 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L29/41783 ,  H01L21/76834 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7851

Abstract: One method disclosed includes forming a final gate structure in a gate cavity that is laterally defined by sidewall spacers, removing a portion of the sidewall spacers to define recessed sidewall spacers, removing a portion of the final gate structure to define a recessed final gate structure and forming an etch stop on the recessed sidewall spacers and the recessed final gate structure. A transistor device disclosed herein includes a final gate structure that has an upper surface positioned at a first height level above a surface of a substrate, sidewall spacers positioned adjacent the final gate structure, the sidewall spacers having an upper surface that is positioned at a second, greater height level above the substrate, an etch stop layer formed on the upper surfaces of the sidewall spacers and the final gate structure, and a conductive contact that is conductively coupled to a contact region of the transistor.

公开(公告)号：US09892926B2

公开(公告)日：2018-02-13

申请号：US15462657

申请日：2017-03-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/28

CPC classification number: H01L29/7856 ,  H01L21/0217 ,  H01L21/28141 ,  H01L21/3212 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/785 ,  H01L29/78654

Abstract: Forming a semiconductor structure includes forming a dummy gate stack on a substrate including a sacrificial spacer on the peripheral of the dummy gate stack. The dummy gate stack is partially recessed. The sacrificial spacer is etched down to the partially recessed dummy gate stack. Remaining portions of the sacrificial spacer are etched leaving gaps on sides of a remaining portion of the dummy gate stack. A first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the remaining portions of the dummy gate stack and extending vertically along a sidewall of a dummy gate cavity. The first and second low-k spacer portions are etched. A poly pull process is performed on the remaining portions of the dummy gate stack. A replacement metal gate (RMG) structure is formed with the first low-k spacer portion and the second low-k spacer portion.

公开(公告)号：US20170117276A1

公开(公告)日：2017-04-27

申请号：US15343776

申请日：2016-11-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/6653 ,  H01L21/2018 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853

Abstract: Semiconductor devices and methods for making the same includes conformally forming a first spacer on multiple fins. A second spacer is conformally formed on the first spacer, the second spacer being formed from a different material from the first spacer. The fins are etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched fins to fill the fin cavity.

公开(公告)号：US09634115B2

公开(公告)日：2017-04-25

申请号：US14301864

申请日：2014-06-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Xiuyu Cai

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L29/4232 ,  H01L21/31144 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/78

Abstract: One illustrative method disclosed herein includes, among other things, forming a first high-k protection layer on the source/drain regions and adjacent the sidewall spacers of a transistor device, removing a sacrificial gate structure positioned between the sidewall spacers so as to thereby define a replacement gate cavity, forming a replacement gate structure in the replacement gate cavity, forming a second high-k protection layer above an upper surface of the spacers, above an upper surface of the replacement gate structure and above the first high-k protection layer, and removing portions of the second high-k protection layer positioned above the first high-k protection layer.

公开(公告)号：US09633906B2

公开(公告)日：2017-04-25

申请号：US14162904

申请日：2014-01-24

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Ali Khakifirooz ,  Theodorus E. Standaert ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L21/84 ,  H01L21/311 ,  H01L29/417

CPC classification number: H01L21/823437 ,  H01L21/31111 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785

Abstract: A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed.

公开(公告)号：US09583597B2

公开(公告)日：2017-02-28

申请号：US13902540

申请日：2013-05-24

Applicant: GLOBALFOUNDRIES, Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L27/0886 ,  H01L29/785 ,  H01L29/7855

Abstract: Asymmetric FinFET devices and methods for fabricating such devices are provided. In one embodiment, a method includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon and depositing a conformal liner over the fin structures. A first portion of the conformal liner is removed, leaving a first space between the fins structures and forming a first metal gate in the first space between the fin structures. A second portion of the conformal liner is removed, leaving a second space between the fin structures and forming a second metal gate in the second space between the fin structures.

Abstract translation: 提供非对称FinFET器件及其制造方法。 在一个实施例中，一种方法包括提供包括形成在其上的多个翅片结构的半导体衬底，并且在翅片结构上沉积保形衬垫。 去除保形衬套的第一部分，在翅片结构之间留下第一空间，并在翅片结构之间的第一空间中形成第一金属浇口。 去除保形衬套的第二部分，在翅片结构之间留下第二空间，并在翅片结构之间的第二空间中形成第二金属浇口。

公开(公告)号：US09564358B1

公开(公告)日：2017-02-07

申请号：US14849269

申请日：2015-09-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/3171 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a semiconductor device includes forming a trench in a passivating layer between neighboring fins. A barrier is formed in the trench. Conductive contacts are formed in the passivating layer to provide electrical connectivity to the fins. The conductive contacts are in direct contact with sidewalls of the barrier. A semiconductor device includes a passivating layer over a pair of fins. A barrier extends through the passivating layer and between the pair of fins and that electrically isolates the fins. Electrical contacts are formed through the passivating layer to the fins. The electrical contacts directly contact sidewalls of the barrier.

Abstract translation: 形成半导体器件的方法包括在相邻散热片之间的钝化层中形成沟槽。 在沟槽中形成屏障。 导电触点形成在钝化层中以提供与鳍片的电连接。 导电触头与屏障的侧壁直接接触。 半导体器件包括在一对鳍上的钝化层。 阻挡层延伸穿过钝化层并在一对翅片之间并且电隔离散热片。 电触头通过钝化层形成到散热片。 电触点直接接触屏障的侧壁。

公开(公告)号：US09543426B2

公开(公告)日：2017-01-10

申请号：US13957587

申请日：2013-08-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L29/78 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636

Abstract: One illustrative method disclosed herein includes removing a portion of a sacrificial sidewall spacer to thereby expose at least a portion of the sidewalls of a sacrificial gate electrode and forming a liner layer on the exposed sidewalls of the sacrificial gate electrode. In this example, the method also includes forming a sacrificial gap fill material above the liner layer, exposing and removing the sacrificial gate electrode to thereby define a gate cavity that is laterally defined by the liner layer, forming a replacement gate structure, removing the sacrificial gap fill material and forming a low-k sidewall spacer adjacent the liner layer. A device is also disclosed that includes a gate cap layer, a layer of silicon nitride or silicon oxynitride positioned on each of two upstanding portions of a gate insulation layer and a low-k sidewall spacer positioned on the layer of silicon nitride or silicon oxynitride.

Abstract translation: 本文公开的一种说明性方法包括去除牺牲侧壁间隔物的一部分，从而暴露牺牲栅电极的侧壁的至少一部分，并在牺牲栅电极的暴露的侧壁上形成衬垫层。 在该示例中，该方法还包括在衬垫层之上形成牺牲间隙填充材料，暴露和去除牺牲栅极电极，从而限定由衬里层横向限定的栅极腔，形成替代栅极结构，去除牺牲层 间隙填充材料并形成邻近衬层的低k侧壁间隔物。 还公开了一种器件，其包括栅极覆盖层，位于栅极绝缘层的两个直立部分中的每一个上的氮化硅或氮氧化硅层，以及位于氮化硅或氮氧化硅层上的低k侧壁间隔物。

公开(公告)号：US09536981B1

公开(公告)日：2017-01-03

申请号：US14868414

申请日：2015-09-29

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Xiuyu Cai ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/0924 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method for fabricating a field effect transistor device comprises forming a fin on a substrate, forming a first dummy gate stack and a second dummy gate stack over the fin, forming spacers adjacent to the fin, the first dummy gate stack, and the second dummy gate stack, etching to remove portions of the fin and form a first cavity partially defined by the spacers, depositing an insulator material in the first cavity, patterning a mask over the first dummy gate stack and portions of the fin, etching to remove exposed portions of the insulator material, and epitaxially growing a first semiconductor material on exposed portions of the fin.

Abstract translation: 一种用于制造场效应晶体管器件的方法，包括在衬底上形成翅片，在鳍片上形成第一虚拟栅极堆叠和第二虚拟栅极堆叠，形成与鳍片相邻的间隔物，第一伪栅极堆叠和第二虚拟栅极 栅极堆叠，蚀刻以去除所述鳍片的部分并形成由所述间隔物部分地限定的第一空腔，在所述第一腔体中沉积绝缘体材料，在第一虚拟栅极堆叠和所述鳍片的部分上图案化掩模，蚀刻以去除暴露部分 并且在所述鳍的暴露部分上外延生长第一半导体材料。

公开(公告)号：US09530775B2

公开(公告)日：2016-12-27

申请号：US13916013

申请日：2013-06-12

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/66795 ,  H01L29/7851

Abstract: One illustrative method disclosed herein includes forming a plurality of trenches in a plurality of active regions of a substrate that defines at least a first plurality of fins and a second plurality of fins for first and second FinFET devices, respectively, forming liner materials adjacent to the first and second plurality of fins, wherein the liner materials adjacent the first fins and the second fins have a different thickness. The method also includes removing insulating material to expose portions of the liner materials, performing an etching process to remove portions of the liner materials so as to expose at least one fin in the first plurality of fins to a first height and at least one of the second plurality of fins to a second height that is different from the first height.

Abstract translation: 本文公开的一种说明性方法包括在衬底的多个有源区域中形成多个沟槽，所述多个有源区域分别限定用于第一和第二FinFET器件的至少第一多个鳍片和第二多个鳍片，以形成邻近 第一和第二多个翅片，其中与第一鳍片和第二鳍片相邻的衬垫材料具有不同的厚度。 该方法还包括去除绝缘材料以暴露衬里材料的部分，执行蚀刻工艺以去除衬里材料的部分，以便将第一组多个鳍中的至少一个翅片暴露于第一高度，并且将至少一个 第二多个翅片到与第一高度不同的第二高度。