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    Buried Interconnect Conductor
    152.
    发明申请
    Buried Interconnect Conductor 审中-公开

    公开(公告)号：US20190035785A1

    公开(公告)日：2019-01-31

    申请号：US15698030

    申请日：2017-09-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

    IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66

    Abstract: Various examples of a buried interconnect line are disclosed herein. In an example, a device includes a fin disposed on a substrate. The fin includes an active device. A plurality of isolation features are disposed on the substrate and below the active device. An interconnect is disposed on the substrate and between the plurality of isolation features such that the interconnect is below a topmost surface of the plurality of isolation features. The interconnect is electrically coupled to the active device. In some such examples, a gate stack of the active device is disposed over a channel region of the active device and is electrically coupled to the interconnect. In some such examples, a source/drain contact is electrically coupled to a source/drain region of the active device, and the source/drain contact is electrically coupled to the interconnect.

    VERTICAL DEVICE ARCHITECTURE
    158.
    发明申请
    VERTICAL DEVICE ARCHITECTURE 有权
    垂直装置架构

    公开(公告)号：US20150380548A1

    公开(公告)日：2015-12-31

    申请号：US14318835

    申请日：2014-06-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Hao Wang ,  Jhon Jhy Liaw ,  Wai-Yi Lien ,  Jia-Chuan You ,  Yi-Hsun Chiu ,  Ching-Wei Tsai ,  Wei-Hao Wu

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

    CPC classification number: H01L29/7827 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/1104 ,  H01L27/11556 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7889 ,  H01L29/7926

    Abstract: The present disclosure relates to a vertical transistor device having rectangular vertical channel bars extending between a source region and a drain region, and an associated method of formation. In some embodiments, the vertical transistor device has a source region disposed over a semiconductor substrate. A channel region with one or more vertical channel bars is disposed over the source region. The one or more vertical channel bars have a bottom surface abutting the source region that has a rectangular shape (i.e., a shape with four sides, with adjacent sides of different length, and four right angles). A gate region is located over the source region at a position abutting the vertical channel bars, and a drain region is disposed over the gate region and the vertical channel bars. The rectangular shape of the vertical channel bars provides for a vertical device having good performance and cell area density.

    Abstract translation: 本公开涉及具有在源极区域和漏极区域之间延伸的矩形垂直沟道条的垂直晶体管器件以及相关联的形成方法。 在一些实施例中，垂直晶体管器件具有设置在半导体衬底上的源极区域。 具有一个或多个垂直通道条的通道区域设置在源极区域上。 一个或多个垂直通道杆具有邻接源区域的底表面，该源区域具有矩形形状（即具有四边的形状，具有不同长度的相邻边和四个直角）。 栅极区域位于邻近垂直沟道条的位置处的源极区域上方，并且漏极区域设置在栅极区域和垂直沟道条的上方。 垂直通道条的矩形形状提供具有良好性能和单元面积密度的垂直装置。

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