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    Apparatus and methods for rate-modulated plasticity in a neuron network
    155.
    发明授权
    Apparatus and methods for rate-modulated plasticity in a neuron network 有权
    神经元网络中速率调制可塑性的装置和方法

    公开(公告)号：US09436908B2

    公开(公告)日：2016-09-06

    申请号：US13774934

    申请日：2013-02-22

    Applicant: QUALCOMM TECHNOLOGIES INC.

    Inventor： Filip Piekniewski ,  Micah Richert ,  Eugene Izhikevich ,  Victor Hokkiu Chan ,  Jeffrey Alexander Levin

    IPC: G06N3/08 ,  G06N3/02 ,  G06N99/00 ,  G06N3/04 ,  G06N3/10

    CPC classification number: G06N3/08 ,  G06N3/02 ,  G06N3/049 ,  G06N3/10 ,  G06N99/005

    Abstract: Apparatus and methods for activity based plasticity in a spiking neuron network adapted to process sensory input. In one approach, the plasticity mechanism of a connection may comprise a causal potentiation portion and an anti-causal portion. The anti-causal portion, corresponding to the input into a neuron occurring after the neuron response, may be configured based on the prior activity of the neuron. When the neuron is in low activity state, the connection, when active, may be potentiated by a base amount. When the neuron activity increases due to another input, the efficacy of the connection, if active, may be reduced proportionally to the neuron activity. Such functionality may enable the network to maintain strong, albeit inactive, connections available for use for extended intervals.

    Abstract translation: 适用于处理感觉输入的加标神经元网络中基于活动的可塑性的装置和方法。 在一种方法中，连接的可塑性机构可以包括因果增强部分和反因果部分。 可以基于神经元的先前活动来配置对应于在神经元响应之后发生的神经元的输入的反因果部分。 当神经元处于低活动状态时，当活动时，连接可能被基础量增强。 当神经元活动由于另一个输入而增加时，如果活动，连接的功效可以与神经元活动成比例地降低。 这样的功能可以使得网络能够维持可用于延长的间隔的强的，虽然是不活动的连接。

    Event-based communication in spiking neuron networks communicating a neural activity payload with an efficacy update
    156.
    发明授权
    Event-based communication in spiking neuron networks communicating a neural activity payload with an efficacy update 有权
    基于事件的通信，在神经元网络中传达神经活动有效载荷与功效更新

    公开(公告)号：US09412064B2

    公开(公告)日：2016-08-09

    申请号：US13868944

    申请日：2013-04-23

    Applicant: QUALCOMM TECHNOLOGIES INC.

    Inventor： Botond Szatmary ,  Micah Richert ,  Oleg Sinyavskiy ,  Eugene Izhikevich

    IPC: G06F15/18 ,  G06N3/04

    CPC classification number: G06N3/049

    Abstract: Apparatus and methods for event based communication in a spiking neuron network. The network may comprise units communicating by spikes via synapses. The spikes may communicate a payload data. The data may comprise one or more bits. The payload may be stored in a buffer of a pre-synaptic unit and be configured to accessed by the post-synaptic unit. Spikes of different payload may cause different actions by the recipient unit. Sensory input spikes may cause postsynaptic response and trigger connection efficacy update. Teaching input spikes trigger the efficacy update without causing the post-synaptic response.

    Abstract translation: 用于加速神经元网络中基于事件的通信的装置和方法。 网络可以包括通过突触通过尖峰通信的单元。 峰值可以传送有效载荷数据。 数据可以包括一个或多个位。 有效载荷可以存储在突触前单元的缓冲器中，并且被配置为由突触后单元访问。 不同有效负载的峰值可能导致接收单元的不同动作。 感觉输入尖峰可能会引起突触后反应并触发连接功效更新。 教学输入尖峰触发功效更新，而不会导致突触后反应。

    Three channel cache-coherency socket protocol
    158.
    发明授权
    Three channel cache-coherency socket protocol 有权

    公开(公告)号：US09361230B2

    公开(公告)日：2016-06-07

    申请号：US14859340

    申请日：2015-09-20

    Applicant: QUALCOMM Technologies Inc.

    Inventor： Jean-Jacques Lecler

    IPC: G06F12/08 ,  G06F13/42 ,  G06F3/06

    CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F13/4282 ,  G06F2212/622

    Abstract: A system and method are disclosed for communicating coherency information between initiator and target agents on semiconductor chips. Sufficient information communication to support full coherency is performed through a socket interface using only three channels. Transaction requests are issued on one channel with responses given on a second. Intervention requests are issued on the same channel as transaction responses. Intervention responses are given on a third channel. Such an approach drastically reduces the complexity of cache coherent socket interfaces compared to conventional approaches. The net effect is faster logic, smaller silicon area, improved architecture performance, and a reduced probability of bugs by the designers of coherent initiators and targets.

    RF device and method for tuning an RF device
    159.
    发明授权
    RF device and method for tuning an RF device 有权
    RF设备和用于调谐RF设备的方法

    公开(公告)号：US09300270B2

    公开(公告)日：2016-03-29

    申请号：US13996853

    申请日：2010-12-23

    Applicant: Zidong Liu ,  Klaus Reimann ,  Kevin R. Boyle ,  Maurice de Jongh ,  Jeroen Bielen

    Inventor： Zidong Liu ,  Klaus Reimann ,  Kevin R. Boyle ,  Maurice de Jongh ,  Jeroen Bielen

    IPC: H03H7/01 ,  H01G5/014 ,  H01G5/019

    CPC classification number: H03H7/0161 ,  H01G5/014 ,  H01G5/019

    Abstract: An RF device includes a substrate and a series circuit of a tunable RF component and a DC blocking capacitor. The series circuit is arranged on the substrate and couples an RF signal terminal to a fixed voltage terminal that is electrically isolated from the RF signal terminal. The tunable RF component is coupled to the RF signal terminal, the DC blocking capacitor is coupled to the fixed voltage terminal and a driver terminal is coupled to the tunable RF component.

    Abstract translation: RF器件包括基底和可调RF元件和隔直流电容器的串联电路。 串联电路布置在基板上，并将RF信号端子耦合到与RF信号端子电隔离的固定电压端子。 可调RF分量耦合到RF信号端，隔直流电容器耦合到固定电压端，驱动端耦合到可调谐RF组件。

    Three channel cache-coherency socket protocol
    160.
    发明授权
    Three channel cache-coherency socket protocol 有权
    三通道缓存一致性套接字协议

    公开(公告)号：US09280468B2

    公开(公告)日：2016-03-08

    申请号：US13659781

    申请日：2012-10-24

    Applicant: QUALCOMM TECHNOLOGIES, INC.

    Inventor： Jean-Jacques Lecler

    IPC: G06F13/38 ,  G06F12/08 ,  G06F13/42 ,  G06F3/00

    CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F13/4282 ,  G06F2212/622

    Abstract: A system and method are disclosed for communicating coherency information between initiator and target agents on semiconductor chips. Sufficient information communication to support full coherency is performed through a socket interface using only three channels. Transaction requests are issued on one channel with responses given on a second. Intervention requests are issued on the same channel as transaction responses. Intervention responses are given on a third channel. Such an approach drastically reduces the complexity of cache coherent socket interfaces compared to conventional approaches. The net effect is faster logic, smaller silicon area, improved architecture performance, and a reduced probability of bugs by the designers of coherent initiators and targets.

    Abstract translation: 公开了用于在半导体芯片上的启动器和目标代理之间传送一致性信息的系统和方法。 通过仅使用三个通道的套接字接口执行足够的信息通信来支持完全一致性。 事务请求是在一个通道上发出的，其中给出响应。 干预请求是在与交易响应相同的频道上发布的。 干预措施在第三个频道上给出。 与传统方法相比，这种方法大大降低了高速缓存一致性套接字接口的复杂性。 净效应是更快的逻辑，更小的硅面积，改进的架构性能，以及由相干启动器和目标的设计者降低错误概率。

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