公开(公告)号：US20240014323A1

公开(公告)日：2024-01-11

申请号：US17903072

申请日：2022-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chen-Wei PAN ,  Sheng CHO

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/06 ,  H01L29/08 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L27/0688 ,  H01L29/0847 ,  H01L21/823431 ,  H01L21/823418

Abstract: A semiconductor device includes a substrate; a fin structure disposed over the substrate; a gate structure disposed over the substrate, wherein an extension direction of the fin structure intersects an extension direction of the gate structure; and a first well disposed under the gate structure, corresponding to an emitter region of the semiconductor device, and having a first conductivity type, wherein the first well is adjacent to a well block layer, and the well block layer is disposed under the gate structure in the emitter region; wherein the well block layer has a first doping concentration of a well implant, the first well has a second doping concentration of the well implant, and the first doping concentration is less than the second doping concentration.

公开(公告)号：US20240014307A1

公开(公告)日：2024-01-11

申请号：US17888523

申请日：2022-08-16

Applicant: United Microelectronics Corp.

Inventor： Wei Jen Chen ,  Kai Lin Lee

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/7786 ,  H01L29/66462 ,  H01L29/42316 ,  H01L29/401

Abstract: A high electron mobility transistor (HEMT) device and a method of forming the HEMT device are provided. The HEMT device includes a substrate, a channel layer, a barrier layer, and a gate structure. The substrate has at least one active region. The channel layer is disposed on the at least one active region. The barrier layer is disposed on the channel layer. The gate structure is disposed on the barrier layer. The gate structure includes a metal layer and a P-type group III-V semiconductor layer vertically disposed between the metal layer and the barrier layer. The P-type group III-V semiconductor layer includes a lower portion and an upper portion on the lower portion, and the upper portion has a top area greater than a top area of the lower portion.

公开(公告)号：US20240014082A1

公开(公告)日：2024-01-11

申请号：US17891090

申请日：2022-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Feng Hsu

IPC: H01L23/13 ,  H01L23/367 ,  H01L23/373 ,  H01L21/48

CPC classification number: H01L23/13 ,  H01L23/3672 ,  H01L23/3733 ,  H01L21/4871

Abstract: The invention provides a semiconductor structure, which comprises a chip comprising a substrate, wherein the substrate has a front surface and a back surface, and the front surface of the substrate comprises a circuit layer, the back surface of the substrate comprises a plurality of microstructures, and a thermal interface material located on the back surface of the substrate, and the thermal interface material contacts the microstructures directly.

公开(公告)号：US11871585B2

公开(公告)日：2024-01-09

申请号：US17389310

申请日：2021-07-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wei Wang ,  Yi-An Shih ,  Huan-Chi Ma

IPC: H10B61/00 ,  H10N50/85

CPC classification number: H10B61/00 ,  H10N50/85

Abstract: A semiconductor device includes a sense amplifier, a first magnetic tunneling junction (MTJ) connected to the sense amplifier at a first distance, a second MTJ connected to the sense amplifier at a second distance, and a third MTJ connected to the sense amplifier at a third distance. Preferably, the first distance is less than the second distance, the second distance is less than the third distance, a critical dimension of the first MTJ is less than a critical dimension of the second MTJ, and the critical dimension of the second MTJ is less than a critical dimension of the third MTJ.

公开(公告)号：US11864473B2

公开(公告)日：2024-01-02

申请号：US17404934

申请日：2021-08-17

Applicant: United Microelectronics Corp.

Inventor： Wen-Jen Wang ,  Chun-Hung Cheng ,  Chuan-Fu Wang

IPC: G11C11/00 ,  H10N70/00 ,  H10B63/00

CPC classification number: H10N70/021 ,  H10B63/80 ,  H10N70/063 ,  H10N70/068 ,  H10N70/841 ,  H10N70/8833

Abstract: Provided is a resistive random-access memory device, including a dielectric layer located on a substrate, a first electrode which is a column located on the dielectric layer, a second electrode covering a top surface and a sidewall of the first electrode, and a variable resistance layer sandwiched between the top surface of the first electrode and the second electrode and between the sidewall of the first electrode and the second electrode and located between the second electrode and the dielectric layer.

公开(公告)号：US11862727B2

公开(公告)日：2024-01-02

申请号：US18090510

申请日：2022-12-29

Applicant: United Microelectronics Corp.

Inventor： Hao Che Feng ,  Hung Jen Huang ,  Hsin Min Han ,  Shih-Wei Su ,  Ming Shu Chiu ,  Pi-Hung Chuang ,  Wei-Hao Huang ,  Shao-Wei Wang ,  Ping Wei Huang

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L29/7854 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/66818

Abstract: The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.

公开(公告)号：US20230420564A1

公开(公告)日：2023-12-28

申请号：US18244892

申请日：2023-09-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shou-Wan Huang ,  Chun-Hsien Lin

IPC: H01L29/78 ,  H01L27/088 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L27/0688 ,  H01L29/0649 ,  H01L29/66795

Abstract: A semiconductor device includes a substrate having a first region and a second region, a first fin-shaped structure extending along a first direction on the first region, a double diffusion break (DDB) structure extending along a second direction to divide the first fin-shaped structure into a first portion and a second portion, and a first gate structure and a second gate structure extending along the second direction on the DDB structure.

公开(公告)号：US20230420292A1

公开(公告)日：2023-12-28

申请号：US18243096

申请日：2023-09-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Chih Chang ,  Yuan-Fu Ko ,  Chih-Sheng Chang

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/02 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L23/528 ,  H01L21/0217 ,  H01L21/02164 ,  H01L23/53295

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a first metal interconnection in the first IMD layer; removing part of the first IMD layer; forming a spacer adjacent to the first metal interconnection; forming a second IMD layer on the spacer and the first metal interconnection; and forming a second metal interconnection in the second IMD layer and on the spacer and the first metal interconnection.

公开(公告)号：US11856867B2

公开(公告)日：2023-12-26

申请号：US17095752

申请日：2020-11-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chun-Hsien Lin ,  Sheng-Yuan Hsueh

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/85 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/20 ,  H10B61/22 ,  H10N50/01 ,  H10N50/85

Abstract: The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a substrate, a first interconnect layer and a second interconnect layer. The first interconnect layer is disposed on the substrate, and the first interconnect layer includes a first dielectric layer around a plurality of first magnetic tunneling junction (MTJ) structures. The second interconnect layer is disposed on the first interconnect layer, and the second interconnect layer includes a second dielectric layer around a plurality of second MTJ structures, wherein, the second MTJ structures and the first MTJ structures are alternately arranged along a direction. The semiconductor device may obtain a reduced size of each bit cell under a permissible process window, so as to improve the integration of components.

公开(公告)号：US11854632B2

公开(公告)日：2023-12-26

申请号：US17502056

申请日：2021-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Hsing Lee ,  Chien-Liang Wu ,  Wen-Kai Lin ,  Te-Wei Yeh ,  Sheng-Yuan Hsueh ,  Chi-Horn Pai

IPC: G11C17/16 ,  G11C16/10 ,  H10B20/25 ,  H10B20/20

CPC classification number: G11C17/165 ,  G11C16/10 ,  H10B20/20 ,  H10B20/25 ,  G11C2216/26

Abstract: A semiconductor memory structure includes a substrate having thereon a transistor forming region and a capacitor forming region. A transistor is disposed on the substrate within the transistor forming region. A capacitor is disposed within the capacitor forming region and electrically coupled to the transistor. A first inter-layer dielectric layer covers the transistor forming region and the capacitor forming region. The first inter-layer dielectric layer surrounds a metal gate of the transistor and a bottom plate of the capacitor. A cap layer is disposed on the first inter-layer dielectric layer. The cap layer has a first thickness within the transistor forming region and a second thickness within the capacitor forming region. The first thickness is greater than the second thickness. The cap layer within the capacitor forming region acts as a capacitor dielectric layer of the capacitor.