公开(公告)号：US09953711B2

公开(公告)日：2018-04-24

申请号：US15638718

申请日：2017-06-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C16/06 ,  G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3445

Abstract: Methods of operating a memory include applying a first voltage level to a first semiconductor material of a first conductivity type forming a channel region for a memory cell of a string of series-connected memory cells, wherein the first semiconductor material is electrically connected to a second semiconductor material of the first conductivity type through a first conductive material of a second conductivity type different than the first conductivity type, and wherein the second semiconductor material forms a channel region for a different memory cell of the string of series-connected memory cells; and applying a second voltage level, less than the first voltage level, to a control gate of the memory cell and applying a third voltage level, less than the second voltage level, to a control gate of the different memory cell while applying the first voltage level to the first semiconductor material.

公开(公告)号：US09910594B2

公开(公告)日：2018-03-06

申请号：US14933874

申请日：2015-11-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shantanu R. Rajwade ,  Pranav Kalavade ,  Toru Tanzawa

IPC: G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/16 ,  G06F13/42

Abstract: Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

公开(公告)号：US09905514B2

公开(公告)日：2018-02-27

申请号：US15095401

申请日：2016-04-11

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L23/48 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/11575 ,  H01L27/11582

Abstract: A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and an opening laterally adjacent a first side of the at least one staircase structure and extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. Conductive structures of the stacked tiers laterally extend from the steps of the at least one staircase structure completely across a second side of the at least one staircase structure opposing the first side to form continuous conductive paths laterally extending completely across the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described.

公开(公告)号：US09881651B2

公开(公告)日：2018-01-30

申请号：US15692512

申请日：2017-08-31

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C5/06 ,  G11C16/26 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11524 ,  G11C16/10 ,  G11C7/22 ,  G11C7/12 ,  G11C5/02 ,  G11C16/16 ,  G11C16/08

CPC classification number: G11C5/063 ,  G11C5/02 ,  G11C5/06 ,  G11C7/12 ,  G11C7/222 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

公开(公告)号：US20170358580A1

公开(公告)日：2017-12-14

申请号：US15670864

申请日：2017-08-07

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/108 ,  H01L27/11 ,  H01L27/11573 ,  H01L27/02 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11531 ,  H01L21/74

CPC classification number: H01L27/108 ,  H01L21/74 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.

公开(公告)号：US20170345506A1

公开(公告)日：2017-11-30

申请号：US15638718

申请日：2017-06-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3445

Abstract: Methods of operating a memory include applying a first voltage level to a first semiconductor material of a first conductivity type forming a channel region for a memory cell of a string of series-connected memory cells, wherein the first semiconductor material is electrically connected to a second semiconductor material of the first conductivity type through a first conductive material of a second conductivity type different than the first conductivity type, and wherein the second semiconductor material forms a channel region for a different memory cell of the string of series-connected memory cells; and applying a second voltage level, less than the first voltage level, to a control gate of the memory cell and applying a third voltage level, less than the second voltage level, to a control gate of the different memory cell while applying the first voltage level to the first semiconductor material.

公开(公告)号：US09773564B2

公开(公告)日：2017-09-26

申请号：US15162238

申请日：2016-05-23

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/32 ,  G11C11/56

CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/32

Abstract: Apparatus and methods are disclosed, including a method that raises an electrical potential of a plurality of access lines to a raised electrical potential, where each access line is associated with a respective charge storage device of a string of charge storage devices. The electrical potential of a selected one of the access lines is lowered, and a data state of the charge storage device associated with the selected access line is sensed while the electrical potential of the selected access line is being lowered. Additional apparatus and methods are described.

公开(公告)号：US20170250190A1

公开(公告)日：2017-08-31

申请号：US15457473

申请日：2017-03-13

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa ,  Tamotsu Murakoshi ,  Deepak Thimmegowda

IPC: H01L27/11556 ,  G11C16/04 ,  H01L27/11521 ,  H01L27/11582 ,  H01L27/11568

Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.

公开(公告)号：US20170229180A1

公开(公告)日：2017-08-10

申请号：US15019175

申请日：2016-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34

Abstract: In an example, a memory device has a first string of memory cells selectively connected to a first data line, a second string of memory cells selectively connected to a second data line, and a transistor that selectively connects the first data line to the second data line.

公开(公告)号：US09728538B2

公开(公告)日：2017-08-08

申请号：US15154335

申请日：2016-05-13

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/108 ,  H01L21/74 ,  H01L27/02 ,  H01L27/11 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11578

CPC classification number: H01L27/108 ,  H01L21/74 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.