公开(公告)号：US10056300B2

公开(公告)日：2018-08-21

申请号：US15729051

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/165 ,  H01L21/265

CPC classification number: H01L21/823821 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545

Abstract: A device includes an NMOS FinFET device including a first fin. The first fin includes a first strain relaxed buffer layer doped with carbon and a first channel semiconductor material formed above the carbon-doped strain relaxed buffer layer. A PMOS FinFET device includes a second fin. The second fin includes a second strain relaxed buffer layer and a second channel semiconductor material formed above the carbon-doped strain relaxed buffer layer. A first gate structure is positioned around a portion of the NMOS fin. A second gate structure is positioned around a portion of the PMOS fin.

公开(公告)号：US10026659B2

公开(公告)日：2018-07-17

申请号：US14608815

申请日：2015-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Murat Kerem Akarvardar ,  Jody A. Fronheiser

IPC: H01L21/00 ,  H01L21/84 ,  H01L29/165 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/02

Abstract: One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing semiconductor material having a first concentration of germanium and a tensile-strained second semiconductor material (having a lesser germanium concentration) positioned on the first germanium-containing semiconductor material and performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of the composite fin structure into a germanium-containing oxide isolation region positioned under the second semiconductor material that is a tensile-strained final fin for an NMOS FinFET device.

公开(公告)号：US09972537B2

公开(公告)日：2018-05-15

申请号：US15052098

申请日：2016-02-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/45 ,  H01L21/02 ,  H01L21/283 ,  H01L29/78 ,  H01L29/165 ,  H01L29/267 ,  H01L27/088 ,  H01L21/84 ,  H01L29/417 ,  H01L27/12

CPC classification number: H01L21/823431 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/283 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/267 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: One illustrative method disclosed herein includes forming a gate structure above a portion of a fin and performing a first epitaxial growth process to form a silicon-carbide (SiC) semiconductor material above the fin in the source and drain regions of a FinFET device. In this example, the method also includes performing a heating process so as to form a source/drain graphene contact from the silicon-carbide (SiC) semiconductor material in both the source and drain regions of the FinFET device and forming first and second source/drain contact structures that are conductively coupled to the source/drain graphene contact in the source region and the drain region, respectively, of the FinFET device.

公开(公告)号：US09954104B2

公开(公告)日：2018-04-24

申请号：US14162948

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ajey Poovannummoottil Jacob

IPC: H01L27/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/20 ,  H01L29/161 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/84 ,  H01L27/12 ,  H01L29/10

CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66795 ,  H01L29/785

Abstract: An improved structure and methods of fabrication for finFET devices utilizing a cladding channel are disclosed. A staircase fin is formed where the fin comprises an upper portion of a first width and a lower portion of a second width, wherein the lower portion is wider than the upper portion. The narrower upper portion allows the cladding channel to be deposited and still have sufficient space for proper gate deposition, while the lower portion is wide to provide improved mechanical stability, which protects the fins during the subsequent processing steps.

公开(公告)号：US20180033700A1

公开(公告)日：2018-02-01

申请号：US15729051

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L21/823821 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66545

Abstract: A device includes an NMOS FinFET device including a first fin. The first fin includes a first strain relaxed buffer layer doped with carbon and a first channel semiconductor material formed above the carbon-doped strain relaxed buffer layer. A PMOS FinFET device includes a second fin. The second fin includes a second strain relaxed buffer layer and a second channel semiconductor material formed above the carbon-doped strain relaxed buffer layer. A first gate structure is positioned around a portion of the NMOS fin. A second gate structure is positioned around a portion of the PMOS fin.

公开(公告)号：US20180026096A1

公开(公告)日：2018-01-25

申请号：US15217643

申请日：2016-07-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Srinivasa R. Banna ,  Deepak K. Nayak ,  Bartlomiej J. Pawlak

IPC: H01L29/06 ,  H01L29/20 ,  H01L21/3065 ,  H01L29/267 ,  H01L21/02 ,  H01L21/308 ,  H01L23/00 ,  H01L29/16

CPC classification number: H01L29/0657 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/3065 ,  H01L21/3083 ,  H01L23/562 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/267

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor wafers with reduced bowing and warping and methods of manufacture. The structure includes a substrate including plurality of trenches which have progressively different depths as they extend radially inwardly from an edge of the substrate towards a center of the substrate.

公开(公告)号：US09865682B2

公开(公告)日：2018-01-09

申请号：US14476918

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/78 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3086 ,  H01L21/31144 ,  H01L29/0649 ,  H01L29/068 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/7851 ,  H01L29/7854

Abstract: A method includes forming at least one fin on a semiconductor substrate. A nanowire material is formed above the fin. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the nanowire material. The nanowire material is etched using the hard mask layer as an etch mask to define a substantially vertical nanowire on a top surface of the at least one fin, wherein at least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.

公开(公告)号：US09824935B2

公开(公告)日：2017-11-21

申请号：US15643036

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L21/8238 ,  H01L29/66 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L21/823821 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66545

Abstract: A method includes forming an initial strain relaxed buffer layer on a semiconductor substrate. A trench is formed within the initial strain relaxed buffer layer. An epitaxial deposition process is performed to form an in situ carbon-doped strain relaxed buffer layer in the trench. A channel semiconductor material is formed on the initial strain relaxed buffer layer and on the in situ carbon-doped strain relaxed buffer layer in the trench. A plurality of fin-formation trenches that extend into the initial strain relaxed buffer layer is formed so as to thereby form an NMOS fin including the channel semiconductor material and the in situ carbon-doped strain relaxed buffer layer and a PMOS fin including the channel semiconductor material and the initial strain relaxed buffer layer. A recessed layer of insulating material and gate structures are formed around the NMOS fin and the PMOS fin.

公开(公告)号：US20170301589A1

公开(公告)日：2017-10-19

申请号：US15643036

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/165 ,  H01L21/265

CPC classification number: H01L21/823821 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66545

Abstract: A method includes forming an initial strain relaxed buffer layer on a semiconductor substrate. A trench is formed within the initial strain relaxed buffer layer. An epitaxial deposition process is performed to form an in situ carbon-doped strain relaxed buffer layer in the trench. A channel semiconductor material is formed on the initial strain relaxed buffer layer and on the in situ carbon-doped strain relaxed buffer layer in the trench. A plurality of fin-formation trenches that extend into the initial strain relaxed buffer layer is formed so as to thereby form an NMOS fin including the channel semiconductor material and the in situ carbon-doped strain relaxed buffer layer and a PMOS fin including the channel semiconductor material and the initial strain relaxed buffer layer. A recessed layer of insulating material and gate structures are formed around the NMOS fin and the PMOS fin.

公开(公告)号：US09754903B2

公开(公告)日：2017-09-05

申请号：US14926880

申请日：2015-10-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Min-hwa Chi ,  Ajey Poovannummoottil Jacob

IPC: H01L21/00 ,  H01L23/62

CPC classification number: H01L23/62 ,  H01L23/5252

Abstract: A semiconductor structure includes a dielectric layer, a silicidable metal layer and an undoped filler material layer are used to create an anti-efuse device. The anti-efuse device may be situated in a dielectric layer of an interconnect structure for a semiconductor device or may be planar. Where part of an interconnect structure, the anti-efuse device may be realized by causing a current to flow therethrough while applying local heating. Where planar, the filler material may be situated between extensions of metal pads and metal atoms caused to move from the extensions to the filler material layer using a current flow and local heating.