公开(公告)号：US20230260876A1

公开(公告)日：2023-08-17

申请号：US17670391

申请日：2022-02-11

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K. Street ,  Kunal R. Parekh

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L21/76898 ,  H01L2225/06541

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material sintering therein.

公开(公告)号：US20230209822A1

公开(公告)日：2023-06-29

申请号：US18117989

申请日：2023-03-06

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Kunal R. Parekh ,  Martin C. Roberts ,  Mohd Kamran Akhtar ,  Chet E. Carter ,  David Daycock

IPC: H10B41/35 ,  H01L21/308 ,  H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L21/67 ,  H01L21/3215 ,  H10B20/00 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B41/35 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/3215 ,  H01L21/31144 ,  H01L21/32155 ,  H01L21/67063 ,  H01L21/76802 ,  H10B20/383 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B43/27 ,  H01L2221/1063 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230134814A1

公开(公告)日：2023-05-04

申请号：US18147342

申请日：2022-12-28

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip ,  Kunal R. Parekh ,  Akira Goda

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A microelectronic device comprises a first die comprising a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, and vertically extending strings of memory cells within the stack structure. The first die further comprises first control logic region comprising a first control logic devices including at least a word line driver. The microelectronic device further comprise a second die attached to the first die, the second die comprising a second control logic region comprising second control logic devices including at least one page buffer device configured to effectuate a portion of control operations of the vertically extending string of memory cells. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US20230051480A1

公开(公告)日：2023-02-16

申请号：US17885374

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Aliasger T. Zaidy ,  Glen E. Hush ,  Sean S. Eilert ,  Kunal R. Parekh

IPC: G11C11/4093 ,  G11C11/4096 ,  G06F3/06 ,  G06F13/16

Abstract: A memory device includes a memory die bonded to a logic die. A logic die that is bonded to a memory die via a wafer-on-wafer bonding process can receive signals indicative of input data from a global data bus of the memory die and through a bond of the logic die and memory die. The logic die can also receive signals indicative of kernel data from local input/output (LIO) lines of the memory die and through the bond. The logic die can perform a plurality of operations at a plurality of vector-vector (VV) units utilizing the signals indicative of input data and the signals indicative of kernel data. The inputs and the outputs to the VV units can be configured based on a mode of the logic die.

公开(公告)号：US20230049683A1

公开(公告)日：2023-02-16

申请号：US17884775

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Sean S. Eilert ,  Aliasger T. Zaidy ,  Glen E. Hush

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L21/78 ,  H01L25/00

Abstract: Methods, systems, and devices related to forming a wafer-on-wafer bond between a memory die and a logic die. A plurality of first metal pads can be formed on a first wafer and a plurality of second metal pads can be formed on a second wafer. A subset of the first metal pads can be bonded to a subset of the second metal pads via a wafer-on-wafer bonding process. Each of a plurality of memory devices on the first wafer can be aligned with and coupled to at least a respective one of a plurality of logic devices on the second wafer. The bonded first and second wafers can be singulated into individual wafer-on-wafer bonded memory and logic dies.

公开(公告)号：US20230048628A1

公开(公告)日：2023-02-16

申请号：US17885269

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Glen E. Hush ,  Sean S. Eilert ,  Aliasger T. Zaidy

IPC: H01L23/00 ,  H01L25/065

Abstract: A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A memory device formed on a memory die can include many global input/output lines and many arrays of memory cells. Each array of memory cells can include respective local input/output (LIO) lines coupled to a global input/output line. A logic device can be formed on a logic die. A bond, formed between the memory die and the logic die via a wafer-on-wafer bonding process, can couple the many global input/output lines to the logic device.

公开(公告)号：US20230048103A1

公开(公告)日：2023-02-16

申请号：US17884781

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh ,  Sean S. Eilert ,  Aliasger T. Zaidy ,  Glen E. Hush

IPC: H01L23/00 ,  H01L25/065

Abstract: Methods, systems, and devices related to a memory die and a logic die having a wafer-on-wafer bond therebetween. A memory die can include a memory array and a plurality of input/output (IO) lines coupled thereto. A logic die can include to a deep learning accelerator (DLA). The memory die can be coupled to the logic die by a wafer-on-wafer bond. The wafer-on-wafer bond can couple the plurality of IO lines to the DLA.

公开(公告)号：US11563018B2

公开(公告)日：2023-01-24

申请号：US16905385

申请日：2020-06-18

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/532 ,  G11C5/06

Abstract: A microelectronic device comprises a memory array region, a control logic region underlying the memory array region, and an interconnect region vertically interposed between the memory array region and the control logic region. The memory array region comprises a stack structure comprising vertically alternating conductive structures and insulating structures; vertically extending strings of memory cells within the stack structure; at least one source structure vertically overlying the stack structure and coupled to the vertically extending strings of memory cells; and digit line structures vertically underlying the stack structure and coupled to the vertically extending strings of memory cells. The control logic region comprises control logic devices for the vertically extending strings of memory cells. The interconnect region comprises structures coupling the digit line structures to the control logic devices. Methods of forming a microelectronic device, and memory devices and electronic systems are also described.

公开(公告)号：US20230005932A1

公开(公告)日：2023-01-05

申请号：US17364281

申请日：2021-06-30

Applicant: Micron Technology, Inc.

Inventor： Fatma Arzum Simsek-Ege ,  Kunal R. Parekh ,  Terrence B. McDaniel ,  Beau D. Barry

IPC: H01L27/108

Abstract: A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, a first isolation material over the first semiconductor structure, and first conductive routing structures over the first semiconductor structure and surrounded by the first isolation material. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material is bonded to the first isolation material to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Control logic devices including transistors comprising portions of the first semiconductor structure are formed after forming the memory cells. Microelectronic devices, electronic systems, and additional methods are also described.

公开(公告)号：US11545456B2

公开(公告)日：2023-01-03

申请号：US16992566

申请日：2020-08-13

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Kunal R. Parekh ,  Aaron S. Yip

IPC: H01L23/00 ,  H01L25/18 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11582

Abstract: A microelectronic device comprises a first die and a second die attached to the first die. The first die comprises a memory array region comprising a stack structure comprising vertically alternating conductive structures and insulative structures, vertically extending strings of memory cells within the stack structure, and first bond pad structures vertically neighboring the vertically extending strings of memory cells. The second die comprises a control logic region comprising control logic devices configured to effectuate at least a portion of control operations for the vertically extending string of memory cells, second bond pad structures in electrical communication with the first bond pad structures, and signal routing structures located at an interface between the first die and the second die. Related microelectronic devices, electronic systems, and methods are also described.