公开(公告)号：US20240387028A1

公开(公告)日：2024-11-21

申请号：US18785858

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: G16H40/20 ,  G06Q10/20 ,  G06Q50/163 ,  G16H40/63 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H04L9/40

Abstract: Methods for performing a pre-clean process to remove an oxide in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a shallow trench isolation region over a semiconductor substrate; forming a gate stack over the shallow trench isolation region; etching the shallow trench isolation region adjacent the gate stack using an anisotropic etching process; and after etching the shallow trench isolation region with the anisotropic etching process, etching the shallow trench isolation region with an isotropic etching process, process gases for the isotropic etching process including hydrogen fluoride and ammonia.

公开(公告)号：US20240363438A1

公开(公告)日：2024-10-31

申请号：US18770919

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66545

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

公开(公告)号：US12022659B2

公开(公告)日：2024-06-25

申请号：US17874844

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H10B51/20 ,  G11C11/22 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H10B43/20 ,  H10B43/27 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  G11C11/2255 ,  H01L23/5226 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/66833 ,  H01L29/78391 ,  H10B43/20 ,  H10B43/27 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

公开(公告)号：US20240194537A1

公开(公告)日：2024-06-13

申请号：US18581182

申请日：2024-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66636

Abstract: A semiconductor device includes a substrate having a first region and a second region of opposite conductivity types, an isolation feature over the substrate, a first fin protruding from the substrate in the first region, a first epitaxial feature over the first fin, a second fin protruding from the substrate in the second region, and a second epitaxial feature over the second fin. The isolation feature includes a first portion disposed on sidewalls of the first fin, a second portion disposed on sidewalls of the second fin, and a third portion located between the first fin and the second fin. The third portion has a thickness larger than the first portion and the second portion.

公开(公告)号：US11862712B2

公开(公告)日：2024-01-02

申请号：US16949728

申请日：2020-11-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Chung-Chi Wen ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for fabricating a semiconductor device that includes a merged source/drain feature extending between two adjacent fin structures. An air gap is formed under the merged source/drain feature. Forming the epitaxial feature includes growing a first epitaxial feature having a first portion over the first fin structure and a second portion over the second fin structure, growing a second epitaxial feature over the first and second portions of the first epitaxial feature, and growing a third epitaxial feature over the second epitaxial feature. The second epitaxial feature includes a merged portion between the first fin structure and the second fin structure.

公开(公告)号：US11856743B2

公开(公告)日：2023-12-26

申请号：US17234201

申请日：2021-04-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Chia-Ta Yu ,  Cheng-Yu Yang ,  Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H10B10/00 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/08 ,  H01L21/027 ,  H01L21/306 ,  H01L21/311 ,  H01L29/66 ,  H01L29/165

CPC classification number: H10B10/12 ,  H01L21/0273 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66636 ,  H10B10/18 ,  H01L21/823814 ,  H01L29/165

Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.

公开(公告)号：US20230387247A1

公开(公告)日：2023-11-30

申请号：US18446190

申请日：2023-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Feng-Cheng Yang ,  Chung-Te Lin ,  Yen-Ming Chen

IPC: H01L29/49 ,  H01L21/311 ,  H01L21/02 ,  H01L29/66 ,  H01L21/302 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/4991 ,  H01L21/311 ,  H01L29/4983 ,  H01L21/02068 ,  H01L29/66583 ,  H01L21/302 ,  H01L29/6653 ,  H01L29/0649 ,  H01L29/41766 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate; two source/drain (S/D) regions over the substrate; a gate stack over the substrate and between the two S/D regions; a spacer layer covering sidewalls of the gate stack; an S/D contact metal over one of the two S/D regions; a first dielectric layer covering sidewalls of the S/D contact metal; and an inter-layer dielectric (ILD) layer covering the first dielectric layer, the spacer layer, and the gate stack, thereby defining a gap. A material of a first sidewall of the gap is different from materials of a top surface and a bottom surface of the gap, and a material of a second sidewall of the gap is different from the materials of the top surface and the bottom surface of the gap.

公开(公告)号：US11791335B2

公开(公告)日：2023-10-17

申请号：US17327123

申请日：2021-05-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te Lin ,  Wei-Yuan Lu ,  Feng-Cheng Yang

IPC: H01L27/088 ,  H01L23/522 ,  H01L23/48 ,  H01L29/06 ,  H01L27/06 ,  H01L29/66 ,  H01L27/11 ,  H01L49/02 ,  H01L21/8234 ,  H10B10/00 ,  H10B61/00 ,  H10N59/00 ,  H01L21/8258

CPC classification number: H01L27/088 ,  H01L21/823475 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/5226 ,  H01L27/0688 ,  H01L28/40 ,  H01L29/0653 ,  H01L29/66545 ,  H10B10/12 ,  H10B61/00 ,  H10N59/00 ,  H01L21/8258 ,  H01L27/0605

Abstract: A method comprises growing an epitaxial layer on a first region of a first wafer while remaining a second region of the first wafer exposed; forming a first dielectric layer over the epitaxial layer and the second region; forming a first transistor on a second wafer; forming a second dielectric layer over the first transistor; bonding the first and second dielectric layers; and forming second and third transistors on the epitaxial layer and on the second region of the first wafer, respectively.

公开(公告)号：US11699737B2

公开(公告)日：2023-07-11

申请号：US17107343

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/51

CPC classification number: H01L29/4991 ,  H01L21/76834 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823864 ,  H01L29/41725 ,  H01L29/495 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66689 ,  H01L29/78 ,  H01L21/823425 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.

公开(公告)号：US11631746B2

公开(公告)日：2023-04-18

申请号：US17121385

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/764 ,  H01L29/08

Abstract: A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening.