公开(公告)号：US10446644B2

公开(公告)日：2019-10-15

申请号：US14745704

申请日：2015-06-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata Camillo-Castillo ,  Hanyi Ding ,  Natalie B. Feilchenfeld ,  Vibhor Jain ,  Anthony K. Stamper

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/06 ,  H01L21/762 ,  H01L29/732

Abstract: Methods for forming a device structure and device structures using a silicon-on-insulator substrate that includes a high-resistance handle wafer. A doped region is formed in the high-resistance handle wafer. A first trench is formed that extends through a device layer and a buried insulator layer of the silicon-on-insulator substrate to the high-resistance handle wafer. The doped region includes lateral extension of the doped region extending laterally of the first trench. A semiconductor layer is epitaxially grown within the first trench, and a device structure is formed using at least a portion of the semiconductor layer. A second trench is formed that extends through the device layer and the buried insulator layer to the lateral extension of the doped region, and a conductive plug is formed in the second trench. The doped region and the plug comprise a body contact.

公开(公告)号：US10446233B2

公开(公告)日：2019-10-15

申请号：US15684492

申请日：2017-08-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor Arsovski ,  Qing Li ,  Xiaoli Hu ,  Wei Zhao ,  Jieyao Liu

IPC: G11C15/04 ,  G11C11/419 ,  G11C7/06 ,  G11C7/12

Abstract: The present disclosure relates to a structure which includes a self-referenced multiplexer circuit which is configured to pre-charge a plurality of sense lines to a voltage threshold in a first time period and sense and detect a value of a selected sense line of the sense lines in a second time period.

公开(公告)号：US20190312603A1

公开(公告)日：2019-10-10

申请号：US15967281

申请日：2018-04-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Abdellatif Bellaouar ,  Sher Jiun Fang ,  Frank Zhang

IPC: H04B1/00 ,  H04B1/16 ,  H03L7/099 ,  H03F3/195 ,  H03G3/30

Abstract: We disclose multiband receivers for millimeter-wave devices, which may have reduced size and/or reduced power consumption. One multiband receiver comprises a first band path comprising a first passive mixer configured to receive a first input RF signal having a first frequency and to be driven by a first local oscillator signal having a frequency about ⅔ the first frequency; a second band path comprising a second passive mixer configured to receive a second input RF signal having a second frequency and to be driven by a second local oscillator signal having a frequency about ⅔ the second frequency; and a base band path comprising a third passive mixer configured to receive intermediate RF signals during a duty cycle and to be driven by a third local oscillator signal having a frequency about ⅓ the first frequency or about ⅓ the second frequency during the duty cycle.

公开(公告)号：US20190311948A1

公开(公告)日：2019-10-10

申请号：US16436117

申请日：2019-06-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. LICAUSI ,  Xunyuan ZHANG

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fully aligned via structures and methods of manufacture. The structure includes: a plurality of minimum ground rule conductive structures formed in a dielectric material each of which comprises a recessed conductive material therein; at least one conductive structure formed in the dielectric material which is wider than the plurality of minimum ground rule conductive structures; an etch stop layer over a surface of the dielectric layer with openings to expose the conductive material of the least one conductive structure and the recessed conductive material of a selected minimum ground rule conductive structure; and an upper conductive material fully aligned with and in direct electrical contact with the at least one conductive structure and the selected minimum ground rule conductive structure, through the openings of the etch stop layer.

公开(公告)号：US20190310399A1

公开(公告)日：2019-10-10

申请号：US15945347

申请日：2018-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil JACOB ,  Yusheng BIAN

IPC: G02B5/18 ,  G02B6/34 ,  G02B6/30

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to grating couplers with structured cladding and methods of manufacture. A structure includes: a grating coupler in a dielectric material; a back end of line (BEOL) multilayer stack over the dielectric material; and a multi-layered cladding structure of alternating materials directly on the BEOL multilayer stack.

公开(公告)号：US10436837B2

公开(公告)日：2019-10-08

申请号：US14886739

申请日：2015-10-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hardik P. Bhagat ,  Mark R. Taylor ,  Baalaji Konda Ramamoorthy ,  Douglas E. Sprague ,  Greeshma Jayakumar

IPC: G01R31/317 ,  G01R31/327

Abstract: A method includes: defining a plurality of clock architecture attributes for a plurality of clock domains to be tested; assigning each one of the plurality of clock domains to a first test group; and refining the assignment of each one of the plurality of clock domains based on the plurality of clock architecture attributes until each of the plurality of clock domains is grouped into a current test group.

公开(公告)号：US20190305105A1

公开(公告)日：2019-10-03

申请号：US15943272

申请日：2018-04-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qun GAO ,  Christopher NASSAR ,  Sugirtha KRISHNAMURTHY ,  Domingo Antonio FERRER LUPPI ,  John SPORRE ,  Shahab SIDDIQUI ,  Beth BAUMERT ,  Abu ZAINUDDIN ,  Jinping LIU ,  Tae Jeong LEE ,  Luigi PANTISANO ,  Heather LAZAR ,  Hui ZANG

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/423

Abstract: A method for controlling the gate length within a FinFET device to increase power performance and the resulting device are provided. Embodiments include forming a vertical gate to extend over a plurality of fins; depositing a respective oxide layer over each of a plurality of skirt regions formed at respective points of intersection of the vertical gate with the plurality of fins; and oxidizing each oxide layer to form a plurality of oxidized gate skirts.

公开(公告)号：US10431665B2

公开(公告)日：2019-10-01

申请号：US15875055

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tao Han ,  Zhenyu Hu ,  Jinping Liu ,  Hsien-Ching Lo ,  Jianwei Peng

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.

公开(公告)号：US10431663B2

公开(公告)日：2019-10-01

申请号：US15867036

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Balasubramanian Pranatharthiharan ,  Pietro Montanini ,  Julien Frougier

IPC: H01L27/12 ,  H01L29/423 ,  H01L27/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L27/088

Abstract: Disclosed are methods for forming an integrated circuit with a nanowire-type field effect transistor and the resulting structure. A sacrificial gate is formed on a multi-layer fin. A sidewall spacer is formed with a gate section on the sacrificial gate and fin sections on exposed portions of the fin. Before or after removal of the exposed portions of the fin, the fins sections of the sidewall spacer are removed or reduced in size without exposing the sacrificial gate. Thus, the areas within which epitaxial source/drain regions are to be formed will not be bound by sidewall spacers. Furthermore, isolation material, which is deposited into these areas prior to epitaxial source/drain region formation and which is used to form isolation elements between the transistor gate and source/drain regions, can be removed without removing the isolation elements. Techniques are also disclosed for simultaneous formation of a nanosheet-type and/or fin-type field effect transistors.

公开(公告)号：US20190295881A1

公开(公告)日：2019-09-26

申请号：US16218868

申请日：2018-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12 ,  H01L27/06 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.