公开(公告)号：US09190486B2

公开(公告)日：2015-11-17

申请号：US13682331

申请日：2012-11-20

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Xunyuan Zhang

IPC: H01L21/76 ,  H01L29/66 ,  H01L29/40 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/28114 ,  H01L29/401 ,  H01L29/4991 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a sacrificial gate structure over a semiconductor substrate. A spacer is formed around the sacrificial gate structure and a dielectric material is deposited over the spacer and semiconductor substrate. The method includes selectively etching the spacer to form a trench between the sacrificial gate structure and the dielectric material. The trench is bounded by a trench surface upon which a replacement spacer material is deposited. The method merges an upper region of the replacement spacer material to enclose a void within the replacement spacer material.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成牺牲栅极结构。 在牺牲栅极结构周围形成间隔物，并且在间隔物和半导体衬底上沉积电介质材料。 该方法包括选择性地蚀刻间隔物以在牺牲栅极结构和电介质材料之间形成沟槽。 沟槽由沟槽表面限定，在该沟槽表面上沉积替代间隔物材料。 该方法合并替换间隔物材料的上部区域以在替换间隔物材料内包围空隙。

公开(公告)号：US09190260B1

公开(公告)日：2015-11-17

申请号：US14540504

申请日：2014-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Xiuyu Cai ,  Seowoo Nam ,  Hyun-Jin Cho

IPC: H01L43/12 ,  H01L21/02 ,  H01L27/22

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L21/02 ,  H01L27/222 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

Abstract: A method of forming a self-aligned MTJ without using a photolithography mask and the resulting device are provided. Embodiments include forming a first electrode over a metal layer, the metal layer recessed in a low-k dielectric layer; forming a MTJ layer over the first electrode; forming a second electrode over the MTJ layer; removing portions of the second electrode, the MTJ layer, and the first electrode down to the low-k dielectric layer; forming a silicon nitride-based layer over the second electrode and the low-k dielectric layer; and planarizing the silicon nitride-based layer down to the second electrode.

Abstract translation: 提供了不使用光刻掩模形成自对准MTJ的方法和所得到的器件。 实施例包括在金属层上形成第一电极，金属层凹入低k电介质层中; 在第一电极上形成MTJ层; 在MTJ层上形成第二电极; 将所述第二电极，所述MTJ层和所述第一电极的部分去除到所述低k电介质层; 在所述第二电极和所述低k电介质层上形成氮化硅基层; 并将氮化硅基层平坦化到第二电极。

公开(公告)号：US09165928B2

公开(公告)日：2015-10-20

申请号：US13918569

申请日：2013-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Kisik Choi

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/42356 ,  H01L29/4975

Abstract: One illustrative method disclosed herein includes forming gate insulation layers and a first metal layer for NMOS and PMOS devices from the same material, selectively forming a first metal layer only for the PMOS device, and forming different shaped metal silicide regions within the NMOS and PMOS gate cavities. A novel integrated circuit product disclosed herein includes an NMOS transistor with an NMOS gate insulation layer, an NMOS metal silicide having a generally rectangular cross-sectional configuration and an NMOS metal layer positioned on the NMOS metal silicide region. The product also includes a PMOS transistor with the same gate insulation material, a first PMOS metal and a PMOS metal silicide region, wherein the NMOS and PMOS metal silicide regions are comprised of the same metal silicide.

Abstract translation: 本文公开的一种说明性方法包括从相同材料形成用于NMOS和PMOS器件的栅极绝缘层和第一金属层，仅选择性地形成用于PMOS器件的第一金属层，以及在NMOS和PMOS栅极内形成不同形状的金属硅化物区域 空腔 本文公开的新型集成电路产品包括具有NMOS栅极绝缘层的NMOS晶体管，具有大致矩形横截面构造的NMOS金属硅化物和位于NMOS金属硅化物区域上的NMOS金属层。 该产品还包括具有相同栅极绝缘材料的PMOS晶体管，第一PMOS金属和PMOS金属硅化物区域，其中NMOS和PMOS金属硅化物区域由相同的金属硅化物组成。

公开(公告)号：US20150294912A1

公开(公告)日：2015-10-15

申请号：US14725663

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L21/8234 ,  H01L21/308 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

公开(公告)号：US20150279971A1

公开(公告)日：2015-10-01

申请号：US14242130

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andy C. Wei

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/66818

Abstract: One method includes forming a plurality of first trenches in a semiconductor substrate to thereby define a plurality of initial fins in the substrate, removing at least one, but less than all, of the plurality of initial fins, forming a fin protection layer on at least the sidewalls of the remaining initial fins, with the fin protection layer in position, performing an etching process to extend a depth of the first trenches to thereby define a plurality of final trenches with a final trench depth, wherein the final trenches define a plurality of final fin structures that each comprise an initial fin, removing the fin protection layer, and forming a recessed layer of insulating material in the final trenches, wherein the recessed layer of insulating material has a recessed surface that exposes a portion of the final fin structures.

Abstract translation: 一种方法包括在半导体衬底中形成多个第一沟槽，从而在衬底中限定多个初始鳍片，去除多个初始鳍片中的至少一个但少于全部的初始鳍片，至少形成鳍片保护层 剩余的初始鳍片的侧壁与翅片保护层在适当的位置，执行蚀刻工艺以延伸第一沟槽的深度，从而限定具有最终沟槽深度的多个最终沟槽，其中最终沟槽限定多个 最终的翅片结构各自包括初始翅片，去除翅片保护层，以及在最终的沟槽中形成绝缘材料的凹陷层，其中绝缘材料的凹陷层具有暴露最终翅片结构的一部分的凹陷表面。

公开(公告)号：US09147730B2

公开(公告)日：2015-09-29

申请号：US14195344

申请日：2014-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/84 ,  H01L29/06 ,  H01L21/306 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L21/3085 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.

Abstract translation: 本文公开的一种说明性方法包括在基底中形成多个初始翅片，其中至少一个初始翅片是待去除翅片，形成与初始翅片相邻的材料，在多个 的初始翅片，通过以下步骤去除所述至少一个待去除的翅片的期望部分：（a）对所述材料执行凹陷蚀刻工艺以去除邻近所述第二侧壁的所述材料定位的部分（但不是全部） 至少一个待去除的翅片，（b）在执行凹陷蚀刻工艺之后，进行翅片凹槽蚀刻工艺以去除待除去的至少一个翅片的部分而不是全部，以及（c）重复步骤 （a）和（b），直到除去所需量的至少一个待去除的翅片。

公开(公告)号：US20150270176A1

公开(公告)日：2015-09-24

申请号：US14219365

申请日：2014-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Ryan Ryoung-Han Kim

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/321 ,  H01L21/285 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/45

CPC classification number: H01L21/823475 ,  H01L21/76807 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/53228 ,  H01L23/53257 ,  H01L27/088 ,  H01L29/665 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a layer of insulating material above first and second transistors, within the layer of insulating material, forming a set of initial device-level contacts for each of the first and second transistors, wherein each set of initial device-level contacts comprises a plurality of source/drain contacts and a gate contact, forming an initial local interconnect structure that is conductively coupled to one of the initial device-level contacts in each of the first and second transistors, and removing the initial local interconnect structure and portions, but not all, of the initial device-level contacts for each the first and second transistors. The method also includes forming a copper local interconnect structure and copper caps above the recessed device-level contacts.

Abstract translation: 一种方法包括在绝缘材料层内的第一和第二晶体管之上形成绝缘材料层，形成用于第一和第二晶体管中的每一个的一组初始器件级触点，其中每组初始器件级触点包括 多个源极/漏极触点和栅极接触，形成初始局部互连结构，其导电耦合到第一和第二晶体管中的每一个中的初始器件级触点之一，以及去除初始局部互连结构和部分， 但不是所有的第一和第二晶体管的初始器件级触点。 该方法还包括在凹入的器件级触点上方形成铜局部互连结构和铜帽。

公开(公告)号：US20150249127A1

公开(公告)日：2015-09-03

申请号：US14195344

申请日：2014-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L29/06 ,  H01L21/311 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L21/3085 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes forming a plurality of initial fins in a substrate, wherein at least one of the initial fins is a to-be-removed fin, forming a material adjacent the initial fins, forming a fin removal masking layer above the plurality of initial fins, removing a desired portion of the at least one to-be-removed fin by: (a) performing a recess etching process on the material to remove a portion, but not all, of the material positioned adjacent the sidewalls of the at least one to-be-removed fin, (b) after performing the recess etching process, performing a fin recess etching process to remove a portion, but not all, of the at least one to be removed fin and (c) repeating steps (a) and (b) until the desired amount of the at least one to-be-removed fin is removed.

Abstract translation: 本文公开的一种说明性方法包括在基底中形成多个初始翅片，其中至少一个初始翅片是待去除翅片，形成与初始翅片相邻的材料，在多个 的初始翅片，通过以下步骤去除所述至少一个待去除的翅片的期望部分：（a）对所述材料执行凹陷蚀刻工艺以去除邻近所述第二侧壁的所述材料定位的部分（但不是全部） 至少一个待去除的翅片，（b）在执行凹陷蚀刻工艺之后，进行翅片凹槽蚀刻工艺以去除待除去的至少一个翅片的部分而不是全部，以及（c）重复步骤 （a）和（b），直到除去所需量的至少一个待去除的翅片。

公开(公告)号：US20150249036A1

公开(公告)日：2015-09-03

申请号：US14195484

申请日：2014-03-03

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/768 ,  H01L23/532 ,  H01L27/088

CPC classification number: H01L27/088 ,  H01L21/76831 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53257 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One example disclosed herein involves forming source/drain conductive contacts to first and second source/drain regions, the first source/drain region being positioned between a first pair of transistor devices having a first gate pitch dimension, the second source/drain region being positioned between a second pair of transistor devices having a second gate pitch dimension that is greater than the first gate pitch dimension, wherein the first and second pairs of transistor devices have a gate structure and sidewall spacers positioned adjacent the gate structure.

Abstract translation: 本文公开的一个示例涉及将源极/漏极导电触点形成到第一和第二源极/漏极区域，第一源极/漏极区域位于具有第一栅极间距尺​​寸的第一对晶体管器件之间，第二源极/漏极区域被定位 在具有大于第一栅极间距尺​​寸的第二栅极间距尺​​寸的第二对晶体管器件之间，其中第一和第二对晶体管器件具有栅极结构和邻近栅极结构定位的侧壁间隔物。

公开(公告)号：US09082852B1

公开(公告)日：2015-07-14

申请号：US14560472

申请日：2014-12-04

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Chun-Chen Yeh

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

Abstract: A FinFET includes a semiconductor fin supporting a first transistor and a second transistor. A first transistor gate electrode extends over a first channel region of the fin and a second transistor gate electrode extends over a second channel region of the fin. Epitaxial growth material on a top of the fin forms a raised source region on a first side of the first transistor gate electrode, an intermediate region between a second side of the first transistor gate electrode and a first side of the second transistor gate electrode, and a raised drain region on a second side of the second transistor gate electrode. The first and second transistor gate electrodes are short circuit connected to each other, with the first transistor configured to have a first threshold voltage and the second transistor configured to have a second threshold voltage different from the first threshold voltage.

Abstract translation: FinFET包括支撑第一晶体管和第二晶体管的半导体鳍片。 第一晶体管栅极电极延伸在鳍片的第一沟道区域上，第二晶体管栅电极在鳍片的第二沟道区域上延伸。 翅片顶部的外延生长材料在第一晶体管栅电极的第一侧上形成升高的源极区，在第一晶体管栅电极的第二侧和第二晶体管栅电极的第一侧之间的中间区域，以及 在所述第二晶体管栅电极的第二侧上的升高的漏极区。 第一和第二晶体管栅极彼此短路，其中第一晶体管被配置为具有第一阈值电压，并且第二晶体管被配置为具有不同于第一阈值电压的第二阈值电压。