公开(公告)号：US12020771B2

公开(公告)日：2024-06-25

申请号：US17818413

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Hyunyoo Lee ,  Kang-Yong Kim ,  Yang Lu

IPC: G11C7/10 ,  H03K19/017 ,  H03K19/173

CPC classification number: G11C7/109 ,  G11C7/1087 ,  H03K19/01742 ,  H03K19/1737

Abstract: Methods, systems, and devices for die location detection for grouped memory dies are described. A memory device may include multiple memory die that are coupled with a shared bus. In some examples, each memory die may include a circuit configured to output an identifier associated with a location of the respective memory die. For example, a first memory die may output a first identifier, based on receiving one or more signals, that identifies a location of the first memory die. Identifying the locations of the respective memory dies may allow for the dies to be individually accessed despite being coupled with a shared bus.

公开(公告)号：US12019570B2

公开(公告)日：2024-06-25

申请号：US18149817

申请日：2023-01-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G06F9/30 ,  G06F12/02 ,  G11C7/22 ,  G11C16/08 ,  G11C16/32 ,  G11C29/02

CPC classification number: G06F13/1689 ,  G06F9/30145 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US11996161B2

公开(公告)日：2024-05-28

申请号：US17805270

申请日：2022-06-03

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim

IPC: G11C7/10 ,  G11C8/10 ,  G11C8/18

CPC classification number: G11C7/1084 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1087 ,  G11C8/10 ,  G11C8/18

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

公开(公告)号：US20240161794A1

公开(公告)日：2024-05-16

申请号：US18407062

申请日：2024-01-08

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyunyoo Lee

IPC: G11C7/10

CPC classification number: G11C7/1063 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093

Abstract: Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory dies that are connected internally thereto. The external connections can be used for transmitting signals indicative of data to and/or from the memory dies while the memory dies in the stack can be connected by a cascading connection for transmission of other signals such as command, address, power, ground, etc.

公开(公告)号：US11947840B2

公开(公告)日：2024-04-02

申请号：US17513311

申请日：2021-10-28

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0673 ,  G11C11/40611 ,  G11C11/40615

Abstract: Described systems, apparatuses, and methods relate to volatile memories that are refreshed to maintain data integrity, such as dynamic random-access memory (DRAM) and synchronous DRAM (SDRAM). A memory device includes multiple dies, with each die having a memory array to be refreshed. The multiple dies may be interconnected via at least one inter-die bus of the memory device. A memory controller sends a command to the memory device to enter a self-refresh mode. In response, a die of the multiple dies can enter the self-refresh mode and initiate or otherwise coordinate refresh operations of the other dies. To do so, the die may transmit at least one refresh-related command to at least one other die using the inter-die bus. Multiple different signaling schemes and timing approaches are disclosed. The described inter-die refresh control principles may be implemented in energy-efficient applications, such as in low-power double data rate (LPDDR) SDRAM.

公开(公告)号：US11922061B2

公开(公告)日：2024-03-05

申请号：US17458068

申请日：2021-08-26

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G11C11/40615

Abstract: Systems, apparatuses, and methods related to a memory device and an associated host device are described. The memory device and the host device can include control logic that allow the memory device and host device to share refresh-timing information, which may allow either the memory device or the host, or both, to manage operations during time that is dedicated to, but unused for, refresh or self-refresh operations. Refresh-timing information shared from the host device may indicate elapsed time since the host device issued a refresh command to the memory device and/or how much time remains before the host device is scheduled to issue another refresh command. Refresh-timing information shared from the memory device may indicate elapsed time since the memory device performed a self-refresh operation and/or how much time remains before the memory device is scheduled to initiate or undergo another self-refresh operation.

公开(公告)号：US20240071461A1

公开(公告)日：2024-02-29

申请号：US17823407

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon ,  Kang-Yong Kim ,  Yang Lu ,  Hyun Yoo Lee

IPC: G11C11/406 ,  G11C11/4096

CPC classification number: G11C11/40622 ,  G11C11/40615 ,  G11C11/4096

Abstract: Described apparatuses and methods relate to adaptive memory registers for a memory system that may support a nondeterministic protocol. To help manage power-delivery networks in a memory system, a device includes logic that can write values to memory registers associated with memory blocks of a memory array. The values indicate whether an associated memory block has been refreshed within a refresh interval. Other logic can read the registers to determine whether a block has been refreshed. The device also includes logic that can access data indicating a row address that was most recently, or is next to be, refreshed and write values representing the address to another register. The register can be read by other logic to determine whether a wordline potentially affected by an activation-based disturb event is near to being refreshed. These techniques can reduce the number of refresh operations performed, saving power and reducing costs.

公开(公告)号：US20240070102A1

公开(公告)日：2024-02-29

申请号：US17823423

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Creston M. Dupree ,  Smruti Subhash Jhaveri ,  Hyun Yoo Lee ,  John Christopher Sancon ,  Kang-Yong Kim ,  Francesco Douglas Verna-Ketel

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4027 ,  G06F13/1668

Abstract: Described apparatuses and methods facilitate bus training with multiple dice, such as multiple memory dice. A controller can communicate with multiple dice to perform bus training by sending a test pattern and receiving in return a feedback pattern indicative of the bits detected by the dice. Because suitable signal timing can differ between dice, even those using the same bus, a controller may train each die separately from the others. In some situations, however, individualized training may be infeasible. To accommodate such situations, logic associated with two or more dice can combine, using at least one logical operation, bits as detected from the test pattern into a combined feedback pattern. A timing parameter that is jointly suitable for multiple dice can be determined, and the bus training may be concluded, responsive to the combined feedback pattern matching the test pattern. The multiple dice may be stacked or linked.

公开(公告)号：US20240070096A1

公开(公告)日：2024-02-29

申请号：US17823432

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Creston M. Dupree ,  Kang-Yong Kim

IPC: G06F13/16 ,  G06F11/07

CPC classification number: G06F13/1689 ,  G06F11/0772 ,  G06F13/1663

Abstract: Described apparatuses and methods relate to erroneous select die access (SDA) detection for a memory system. A memory system may include a memory controller and a memory device that are capable of implementing an SDA protocol that enables selective memory die access to multiple memory devices that couple to a command bus. A memory device can include logic that determines if signaling that conflicts with the SDA protocol is detected. If it is determined that conflicting signaling is detected, the logic may provide an indication of the conflicted signaling. In doing so, the erroneous SDA detection described herein may reduce the likelihood of a memory device erroneously masking memory dice, thereby limiting the memory device from exhibiting unexpected, and in some cases, dangerous behavior.

公开(公告)号：US20240070093A1

公开(公告)日：2024-02-29

申请号：US17823443

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Hyun Yoo Lee ,  Kang-Yong Kim ,  Jason McBride Brown ,  Venkatraghavan Bringivijayaraghavan ,  Vijayakrishna J. Vankayala

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G06F13/1621 ,  G06F13/1689 ,  G06F13/4068

Abstract: Apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies are described. The asymmetric read-write sequence refers to an asymmetric die-access sequence for read versus write operations. The “asymmetric” term refers to a difference in an order in which data is written to or read from interface and linked dies of the interconnected die architecture. The orders for the read and write operations can be chosen such that a delay associated with transferring data between the interconnected dies occurs as data passes between the interface die and a memory controller. With asymmetric read-write burst sequences, overall timing of the read and write operations of a memory device may be impacted less, if at all, by a timing delay associated with the interconnected die architecture.