公开(公告)号：US11158638B2

公开(公告)日：2021-10-26

申请号：US16613478

申请日：2018-05-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato

IPC: H01L29/10 ,  H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device capable of retaining data for a long period is provided. The semiconductor device includes a first memory cell and a second memory cell. The first memory cell includes a first transistor. The second memory cell includes a second transistor. The threshold voltage of the second transistor is higher than the threshold voltage of the first transistor. The first transistor includes a first metal oxide. The second transistor includes a second metal oxide. Each of the first metal oxide and the second metal oxide includes a channel formation region. Each of the first metal oxide and the second metal oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn. The atomic ratio of the element M to In in the second metal oxide is greater than that in the first metal oxide.

公开(公告)号：US11031403B2

公开(公告)日：2021-06-08

申请号：US16605548

申请日：2018-04-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Daisuke Matsubayashi ,  Kiyoshi Kato ,  Katsuaki Tochibayashi ,  Shuhei Nagatsuka

IPC: H01L27/108 ,  H01L27/1156 ,  H01L27/06 ,  H01L29/786 ,  H01L21/311 ,  H01L27/32 ,  H01L27/12

Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes a first transistor, a second transistor, a first capacitor, and a second capacitor. The first transistor includes an oxide over a first insulator, a second insulator over the oxide, a first conductor over the second insulator, a third insulator over the first conductor, a fourth insulator in contact with the second insulator, the first conductor, and the third insulator, and a fifth insulator in contact with the fourth insulator. The second transistor includes an oxide over the first insulator, a sixth insulator over the oxide, a second conductor over the sixth insulator, a seventh insulator over the second conductor, an eighth insulator in contact with the sixth insulator, the second conductor, and the seventh insulator, and a ninth insulator in contact with the eighth insulator. The first capacitor includes an oxide, a tenth insulator over the oxide, and a third conductor over the tenth insulator. The second capacitor includes an oxide, an eleventh insulator over the oxide, and a fourth conductor over the eleventh insulator.

公开(公告)号：US11011542B2

公开(公告)日：2021-05-18

申请号：US16786273

申请日：2020-02-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hajime Kimura ,  Takanori Matsuzaki ,  Kiyoshi Kato ,  Satoru Okamoto

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/24 ,  H01L29/51

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

公开(公告)号：US10593693B2

公开(公告)日：2020-03-17

申请号：US16004890

申请日：2018-06-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hajime Kimura ,  Takanori Matsuzaki ,  Kiyoshi Kato ,  Satoru Okamoto

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/24 ,  H01L29/51

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

公开(公告)号：US10324521B2

公开(公告)日：2019-06-18

申请号：US15299579

申请日：2016-10-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuji Nishijima ,  Hidetomo Kobayashi ,  Tomoaki Atsumi ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: G06F1/3296 ,  G06F1/3234 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/32

Abstract: A microcontroller which operates in a low power consumption mode is provided. A microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register in the peripheral circuit is provided in an interface with a bus line. A power gate for controlling supply control is provided. The microcontroller can operate not only in a normal operation mode where all circuits are active, but also in a low power consumption mode where some of the circuits are active. A volatile memory and nonvolatile memory are provided in a register, such as a register of the CPU. Data in the volatile memory is backed up in the nonvolatile memory before the power supply is stopped. In the case where the operation mode returns to the normal mode, when power supply is started again, data in the nonvolatile memory is written back into the volatile memory.

公开(公告)号：US10304523B2

公开(公告)日：2019-05-28

申请号：US14705698

申请日：2015-05-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Tatsuya Onuki

IPC: G11C11/4096 ,  G11C11/4091 ,  G11C11/4097

Abstract: A memory device with low power consumption is provided. The memory device includes a sense amplifier, bit lines, memory cells, and first transistors. The bit lines are provided over a layer comprising the sense amplifier. The memory cells are provided over a layer comprising the bit lines. The memory cell includes a second transistor and a capacitor. The sense amplifier and the bit lines are electrically connected to each other through the first transistors. The sense amplifier may include at least one layer of a conductor.

公开(公告)号：US10236875B2

公开(公告)日：2019-03-19

申请号：US15482985

申请日：2017-04-10

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Yutaka Shionoiri ,  Takanori Matsuzaki

IPC: H03K17/687 ,  G11C5/02 ,  G11C7/06 ,  H01L29/26 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4097 ,  H03K19/0944 ,  H02M3/07

Abstract: A potential is held stably. A negative potential is generated with high accuracy. A semiconductor device with a high output voltage is provided. The semiconductor device includes a first transistor, a second transistor, a capacitor, and a comparator. The comparator includes a non-inverting input terminal, an inverting input terminal, and an output terminal. A gate and one of a source and a drain of the first transistor are electrically connected to each other. One of a source and a drain of the second transistor is electrically connected to the non-inverting input terminal of the comparator, one electrode of the capacitor, and a gate of the second transistor. The other of the source and the drain of the second transistor is electrically connected to the one of the source and the drain of the first transistor. The first transistor and the second transistor each contain an oxide semiconductor.

公开(公告)号：US10141344B2

公开(公告)日：2018-11-27

申请号：US15811879

申请日：2017-11-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Yuta Endo ,  Ryo Tokumaru

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/443 ,  H01L21/4757 ,  H01L27/108 ,  H01L29/10 ,  H01L29/786 ,  H01L29/423

Abstract: A semiconductor device having favorable electric characteristics is provided. The semiconductor device includes a first transistor and second transistor. The first transistor includes a first conductor over a substrate; a first insulator thereover; a first oxide thereover; a second insulator over thereover; a second conductor including a side surface substantially aligned with a side surface of the second insulator and being over the second insulator; a third insulator including a side surface substantially aligned with a side surface of the second conductor and being over the second conductor; a fourth insulator in contact with a side surface of the second insulator, a side surface of the second conductor, and a side surface of the third insulator; and a fifth insulator in contact with the first oxide and the fourth insulator. The second transistor includes a third conductor; a fourth conductor at least part of which overlaps with the third conductor; and a second oxide between the third conductor and the fourth conductor. The third conductor and the fourth conductor are electrically connected to the first conductor.

公开(公告)号：US10083995B2

公开(公告)日：2018-09-25

申请号：US15598651

申请日：2017-05-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Satoshi Murakami ,  Masahiko Hayakawa ,  Kiyoshi Kato ,  Mitsuaki Osame

IPC: H01L27/12 ,  H01L33/52 ,  G02F1/1362 ,  H01L27/32 ,  H01L27/13 ,  H01L51/52

CPC classification number: H01L27/1248 ,  G02F1/136227 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1255 ,  H01L27/13 ,  H01L27/3246 ,  H01L27/3276 ,  H01L33/52 ,  H01L51/5237 ,  H01L51/5253

Abstract: It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially by etching to expose an active layer of the TFT.

公开(公告)号：US10074663B2

公开(公告)日：2018-09-11

申请号：US15278546

申请日：2016-09-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: H01L21/336 ,  H01L27/11551 ,  G11C16/04 ,  H01L27/06 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/12 ,  H01L49/02 ,  H01L29/04 ,  H01L29/16 ,  H01L29/24 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L27/1207 ,  G11C16/0466 ,  H01L27/0688 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60 ,  H01L29/04 ,  H01L29/16 ,  H01L29/24 ,  H01L29/78 ,  H01L29/7869

Abstract: An object is to provide a semiconductor device having a novel structure with a high degree of integration. A semiconductor device includes a semiconductor layer having a channel formation region, a source electrode and a drain electrode electrically connected to the channel formation region, a gate electrode overlapping with the channel formation region, and a gate insulating layer between the channel formation region and the gate electrode. A portion of a side surface of the semiconductor layer having the channel formation region and a portion of a side surface of the source electrode or the drain electrode are substantially aligned with each other when seen from a planar direction.