公开(公告)号：US20150357983A1

公开(公告)日：2015-12-10

申请号：US14296914

申请日：2014-06-05

Applicant: STMICROELECTRONICS, INC.

Inventor： Davy Choi

IPC: H03G1/00 ,  H03F1/02 ,  H03F3/45

CPC classification number: H03G3/02 ,  H03F1/0205 ,  H03F1/26 ,  H03F3/3022 ,  H03F3/393 ,  H03F3/45 ,  H03F3/45094 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2200/261 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03F2203/45336 ,  H03G1/0035 ,  H03G1/02 ,  H03G3/3036 ,  H03M1/18

Abstract: An instrumentation amplifier includes first and second resistors for gain setting. The operational amplifiers within the instrumentation amplifier include selectively enabled current drive sources coupled to the amplifier output. The first and second resistors have variable resistances. A control circuit is configured to select the variable resistances of the first and second resistors to implement a fixed gain for the instrumentation amplifier and further selectively enable the current drive sources. The control circuit receives an indication of a downstream programmable gain (for example, from a downstream programmable gain amplifier). The variable resistances of the first and second resistors are selected to be scaled inversely with respect to the downstream programmable gain and the current drive sources are enabled proportionately with respect to the downstream programmable gain.

Abstract translation: 仪表放大器包括用于增益设定的第一和第二电阻器。 仪表放大器内的运算放大器包括耦合到放大器输出的有选择地使能的电流驱动源。 第一和第二电阻具有可变电阻。 控制电路被配置为选择第一和第二电阻器的可变电阻以实现仪器放大器的固定增益，并且进一步选择性地启用当前的驱动源。 控制电路接收下游可编程增益的指示（例如，从下游可编程增益放大器）。 第一和第二电阻器的可变电阻被选择为相对于下游可编程增益反相缩放，并且当前驱动源相对于下游可编程增益成比例地启用。

公开(公告)号：US20150357425A1

公开(公告)日：2015-12-10

申请号：US14297822

申请日：2014-06-06

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

公开(公告)号：US20150349085A1

公开(公告)日：2015-12-03

申请号：US14288766

申请日：2014-05-28

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Ruilong XIE ,  Xiuyu CAI ,  Chun-chen YEH

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

Abstract translation: 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片。 在半导体鳍片的端部附近和相邻的半导体鳍片之间的空间内形成至少一个电介质层。 在半导体翅片的端部处邻近最外半导体翅片形成一对侧壁间隔物。 去除该对侧壁间隔物之间​​的至少一个电介质层和半导体翅片的端部。 源极/漏极区域形成在该对侧壁间隔物之间​​。

公开(公告)号：US20150348879A1

公开(公告)日：2015-12-03

申请号：US14293364

申请日：2014-06-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson TALLEDO

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/4825 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8385 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor device may include an IC, and lead frame contact areas adjacent the IC. Each lead frame contact area may have a lead opening. The semiconductor device may include bond wires, each bond wire coupling a respective lead frame contact area with the IC. The semiconductor device may include encapsulation material surrounding the IC, the lead frame contact areas, and the bond wires, and leads. Each lead may extend through a respective lead opening and outwardly from the encapsulation material.

Abstract translation: 半导体器件可以包括IC，以及与IC相邻的引线框架接触区域。 每个引线框接触区域可以具有引线开口。 半导体器件可以包括接合线，每个接合线将相应的引线框架接触区域与IC耦合。 半导体器件可以包括围绕IC的封装材料，引线框架接触区域和接合线以及引线。 每个引线可以延伸通过相应的引线开口并且从封装材料向外延伸。

公开(公告)号：US09202919B1

公开(公告)日：2015-12-01

申请号：US14447685

申请日：2014-07-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Kejia Wang ,  Chun-chen Yeh

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7848

Abstract: Techniques and structures for shaping the source and drain junction profiles of a finFET are described. A fin may be partially recessed at the source and drain regions of the finFET. The partially recessed fin may be further recessed laterally and vertically, such that the laterally recessed portion extends under at least a portion of the finFET's gate structure. Source and drain regions of the finFET may be formed by growing a buffer layer on the etched surfaces of the fin and/or growing a source and drain layer at the source and drain regions of the fin. The lateral recess can improve channel-length uniformity along the height of the fin.

Abstract translation: 描述了用于成形finFET的源极和漏极结线廓的技术和结构。 翅片可以部分地凹陷在finFET的源极和漏极区域。 部分凹入的翅片可以进一步侧向和垂直地凹入，使得横向凹入部分在finFET的栅极结构的至少一部分下方延伸。 可以通过在鳍的蚀刻表面上生长缓冲层和/或在鳍的源极和漏极区生长源极和漏极层来形成鳍FET的源区和漏极区。 横向凹槽可以改善沿翅片高度的通道长度均匀性。

公开(公告)号：US20150333155A1

公开(公告)日：2015-11-19

申请号：US14281021

申请日：2014-05-19

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  RUILONG XIE ,  XIUYU CAI ,  CHUN-CHEN YEH ,  KEJIA WANG

IPC: H01L29/66 ,  H01L27/088

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.

Abstract translation: 制造半导体器件的方法可以包括：形成第一和第二间隔开的半导体有源区域，其间具有绝缘区域，形成在第一和第二间隔开的半导体有源区域之间并在绝缘区域上延伸的至少一个牺牲栅极线，以及形成 在所述至少一个牺牲栅极线的相对侧上的侧壁间隔物。 该方法还可以包括去除侧壁间隔物内的至少一个牺牲栅极线的部分，并且在绝缘区域的上方限定限定至少一个栅极端部凹部的部分，用电介质材料填充至少一个栅极端部凹部，并且形成相应的 替代栅极代替在第一和第二间隔开的半导体有源区之上的至少一个牺牲栅极线的部分。

公开(公告)号：US20150323944A1

公开(公告)日：2015-11-12

申请号：US14270677

申请日：2014-05-06

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS S.R.L.

Inventor： Tom Youssef ,  Alessandro Gasparini ,  Yamu Hu ,  Naren K. Sahoo ,  Anthony Junior Casillan

IPC: G05F1/10

CPC classification number: G05F1/561 ,  G05F1/10

Abstract: A modulated digital input signal is passed through a conditioning circuit to generate a first input signal. An error amplifier circuit receives the first input signal and a second input signal, and controls the operation of a MOS transistor to generate an output signal that is current modulated. The output signal is sensed to generate a feedback signal. A switching circuit selectively applies the feedback signal as the second input signal in response to a transition of the modulated digital input signal from a first logic state to a second logic state. The switching circuit alternatively selectively applies a fixed reference signal as the second input signal to the error amplifier in response to a transition of the modulated digital input signal from the second logic state to the first logic state.

Abstract translation: 调制数字输入信号通过调理电路以产生第一输入信号。 误差放大器电路接收第一输入信号和第二输入信号，并且控制MOS晶体管的操作以产生电流调制的输出信号。 感测输出信号以产生反馈信号。 响应于调制的数字输入信号从第一逻辑状态到第二逻辑状态的转变，开关电路选择性地将反馈信号作为第二输入信号施加。 响应于调制的数字输入信号从第二逻辑状态到第一逻辑状态的转变，开关电路交替地选择性地将固定参考信号作为第二输入信号施加到误差放大器。

公开(公告)号：US09148311B2

公开(公告)日：2015-09-29

申请号：US13284879

申请日：2011-10-29

Applicant: Muralidhar Karthik ,  George A. Vlantis

Inventor： Muralidhar Karthik ,  George A. Vlantis

IPC: H04K1/10 ,  H04L25/02 ,  H04L25/03 ,  H04L27/26

CPC classification number: H04L25/022 ,  H04L25/0204 ,  H04L25/0224 ,  H04L25/03821 ,  H04L27/2601

Abstract: In an embodiment, a channel estimator includes first, second, and third stages. The first stage is configurable to generate a first observation scalar for a first communication path of a first communication channel, and the second stage is configurable to generate a second observation scalar for a first communication path of a second communication channel. And the third stage is configurable to generate channel-estimation coefficients in response to the first and second observation scalars. For example, such a channel estimator may use a recursive algorithm, such as a Vector State Scalar Observation (VSSO) Kalman algorithm, to estimate the responses of channels over which propagate simultaneous orthogonal-frequency-division-multiplexed (OFDM) signals (e.g., MIMO-OFDM signals) that suffer from inter-carrier interference (ICI) due to Doppler spread. Such a channel estimator may estimate the channel responses more accurately, more efficiently, with a less-complex algorithm, and with less-complex software or circuitry, than conventional channel estimators.

Abstract translation: 在一个实施例中，信道估计器包括第一，第二和第三阶段。 第一级可配置为生成第一通信信道的第一通信路径的第一观察标量，并且第二级可配置为生成第二通信信道的第一通信路径的第二观察标量。 并且第三阶段可配置为响应于第一和第二观测标量产生信道估计系数。 例如，这样的信道估计器可以使用诸如矢量状态标量观测（VSSO）卡尔曼算法的递归算法来估计传播的同时正交频分复用（OFDM）信号（例如， MIMO-OFDM信号），其由于多普勒扩展而受到载波间干扰（ICI）的影响。 这样的信道估计器可以比传统的信道估计器更精确地，更有效地利用较不复杂的算法和不太复杂的软件或电路来估计信道响应。

公开(公告)号：US20150270398A1

公开(公告)日：2015-09-24

申请号：US14223373

申请日：2014-03-24

Applicant: STMicroelectronics, Inc. ,  Globalfoundries Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L21/28 ,  H01L21/308 ,  H01L29/66 ,  H01L29/51

CPC classification number: H01L29/7848 ,  H01L21/28194 ,  H01L21/3085 ,  H01L29/0847 ,  H01L29/515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7849 ,  H01L29/785

Abstract: One method disclosed includes, among other things, forming a fin structure comprised of a semiconductor material, a first epi semiconductor material and a second epi semiconductor material, forming a sacrificial gate structure above the fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one etching process to remove the portions of the fin structure positioned laterally outside of the sidewall spacer so as to thereby define a fin cavity in the source/drain regions of the device and to expose edges of the fin structure positioned under the sidewall spacer, and performing an epitaxial deposition process to form an epi etch stop layer on the exposed edges of the fin structure positioned under the sidewall spacer and within the fin cavity.

Abstract translation: 所公开的一种方法包括形成由半导体材料，第一外延半导体材料和第二外延半导体材料构成的鳍状结构，在鳍状结构之上形成牺牲栅极结构，形成邻近牺牲栅极结构的侧壁间隔物 执行至少一个蚀刻工艺以去除位于侧壁间隔件外侧的翅片结构的部分，从而在该装置的源极/漏极区域中限定翅片空腔并且暴露位于该侧壁间隔之下的翅片结构的边缘 并且执行外延沉积工艺以在位于侧壁间隔件下方和翅片腔内的翅片结构的暴露边缘上形成外延蚀刻停止层。

公开(公告)号：US20150255605A1

公开(公告)日：2015-09-10

申请号：US14201555

申请日：2014-03-07

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Ali Khakifirooz ,  Pierre Morin ,  Sanjay C. Mehta

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods and structures for increasing strain in fully insulated finFETs are described. The finFET structures may be formed on an insulating layer and include source, channel, and drain regions that are insulated all around. During fabrication, the source and drain regions may be formed as suspended structures. A strain-inducing material may be formed around the source and drain regions on four contiguous sides so as to impart strain to the channel region of the finFET.

Abstract translation: 描述了在全绝缘finFET中增加应变的方法和结构。 finFET结构可以形成在绝缘层上，并且包括绝缘的源极，沟道和漏极区域。 在制造期间，源区和漏区可以形成为悬挂结构。 应变诱导材料可以在四个相邻侧面上的源极和漏极区域周围形成，以便对finFET的沟道区域施加应力。