公开(公告)号：US20170018630A1

公开(公告)日：2017-01-19

申请号：US14800381

申请日：2015-07-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONS ,  STMicroelectronics, Inc.

Inventor： Hong He ,  Nicolas Loubet ,  Junli Wang

IPC: H01L29/66 ,  H01L29/167 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/2256 ,  H01L21/31116 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66818

Abstract: A method for channel formation in a fin transistor includes removing a dummy gate and dielectric from a dummy gate structure to expose a region of an underlying fin and depositing an amorphous layer including Ge over the region of the underlying fin. The amorphous layer is oxidized to condense out Ge and diffuse the Ge into the region of the underlying fin to form a channel region with Ge in the fin.

Abstract translation: 用于在鳍式晶体管中形成通道的方法包括从虚拟栅极结构去除伪栅极和电介质以暴露下面的鳍片的区域，并且在下面的鳍片的区域上沉积包括Ge的非晶层。 将非晶层氧化以凝结出Ge并将Ge扩散到下面的翅片的区域中以在翅片中形成具有Ge的沟道区域。

公开(公告)号：US20170018465A1

公开(公告)日：2017-01-19

申请号：US15220150

申请日：2016-07-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Hong He ,  James Kuss ,  Nicolas Loubet ,  Junli Wang

IPC: H01L21/84 ,  H01L27/092 ,  H01L21/02 ,  H01L29/161 ,  H01L21/306 ,  H01L21/324 ,  H01L27/12 ,  H01L21/8238

CPC classification number: H01L21/845 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/161

Abstract: A method for forming fins includes growing a SiGe layer and a silicon layer over a surface of a bulk Si substrate, patterning fin structures from the silicon layer and the SiGe layer and filling between the fin structures with a dielectric fill. Trenches are formed to expose end portions of the fin structures. A first region of the fin structures is blocked off. The SiGe layer of the fin structures of a second region is removed by selectively etching the fin structures from the end portions to form voids, which are filled with dielectric material. The silicon layer of the fin structures is exposed. The SiGe layer in the first region is thermally oxidized to drive Ge into the silicon layer to form SiGe fins on an oxide layer in the first region and silicon fins on the dielectric material in the second region.

Abstract translation: 用于形成翅片的方法包括在体Si衬底的表面上生长SiGe层和硅层，从硅层和SiGe层图案化翅片结构，并用电介质填充物填充翅片结构。 形成沟槽以暴露翅片结构的端部。 翅片结构的第一个区域被阻挡。 通过从端部选择性地蚀刻翅片结构来去除第二区域的翅片结构的SiGe层，以形成填充有电介质材料的空隙。 翅片结构的硅层被暴露。 第一区域中的SiGe层被热氧化以将Ge驱动到硅层中，以在第一区域中的氧化物层上形成SiGe散热片，并在第二区域中在介电材料上形成硅散热片。

公开(公告)号：US09548222B2

公开(公告)日：2017-01-17

申请号：US14047144

申请日：2013-10-07

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L21/67

CPC classification number: H01L21/02057 ,  B08B3/08 ,  B08B3/12 ,  H01L21/67028 ,  H01L21/67046

Abstract: A brush-cleaning apparatus is disclosed for use in cleaning a semiconductor wafer after polishing. Embodiments of the brush-cleaning apparatus implemented with a multi-branch chemical dispensing unit are applied beneficially to clean semiconductor wafers, post-polish, using a hybrid cleaning method. An exemplary hybrid cleaning method employs a two-chemical sequence in which first and second chemical treatment modules are separate from one another, and are followed by a pH-neutralizing-rinse that occurs in a treatment module separate from the first and second chemical treatment modules. Implementation of such hybrid methods is facilitated by the multi-branch chemical dispensing unit, which provides separate chemical lines to different chemical treatment modules, and dispenses chemical to at least four different areas of each wafer during single-wafer processing in an upright orientation. The multi-branch chemical dispensing unit provides a flexible, modular building block for constructing various equipment configurations that use multiple chemical treatments and/or pH neutralization steps.

Abstract translation: 公开了用于清洁抛光后的半导体晶片的刷子清洁装置。 使用多分支化学分配单元实施的刷子清洁装置的实施例有利地应用混合清洗方法来清洁半导体晶片，后抛光。 示例性的混合清洁方法采用其中第一和第二化学处理组件彼此分离的双化学序列，然后是在与第一和第二化学处理模块分离的处理模块中发生的pH中和漂洗 。 这种混合方法的实现通过多分支化学分配单元来实现，该分支化学分配单元向不同的化学处理模块提供单独的化学品流，并且在直立取向的单晶片处理期间将化学品分配给每个晶片的至少四个不同区域。 多分支化学分配单元提供了一种灵活的模块化构建块，用于构建使用多种化学处理和/或pH中和步骤的各种设备配置。

公开(公告)号：US20170012061A1

公开(公告)日：2017-01-12

申请号：US15274403

申请日：2016-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Wai-Kin Li ,  Chieh-Yu Lin ,  Yannick Daurelle

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/84 ,  H01L27/02 ,  H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/528

CPC classification number: H01L27/1211 ,  H01L21/441 ,  H01L21/7624 ,  H01L21/76807 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/40

Abstract: A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.

Abstract translation: 半导体器件包括形成在半导体衬底上的多个栅极，其包括多个外部有源区域（例如CMOS / PMOS区域，源极/漏极区域等）和一个或多个内部有源区域。 隔离器形成在与一个或多个内部有源区域相关联的一个或多个内部门上。 接触杆电连接外部有源区域和/或外部门，并形成在隔离器上。 隔离器将接触杆与一个或多个内部有源区域和/或一个或多个内部门隔离。

公开(公告)号：US20170005169A1

公开(公告)日：2017-01-05

申请号：US14755663

申请日：2015-06-30

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L29/10 ,  H01L29/161 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L27/0886 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/41791 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7849 ,  H01L2029/7858

Abstract: A self-aligned SiGe FinFET device features a relaxed channel region having a high germanium concentration. Instead of first introducing germanium into the channel and then attempting to relax the resulting strained film, a relaxed channel is formed initially to accept the germanium. In this way, a presence of germanium can be established without straining or damaging the lattice. Gate structures are patterned relative to intrinsic silicon fins, to ensure that the gates are properly aligned, prior to introducing germanium into the fin lattice structure. After aligning the gate structures, the silicon fins are segmented to elastically relax the silicon lattice. Then, germanium is introduced into the relaxed silicon lattice, to produce a SiGe channel that is substantially stress-free and also defect-free. Using the method described, concentration of germanium achieved in a structurally stable film can be increased to a level greater than 85%.

Abstract translation: 自对准SiGe FinFET器件具有具有高锗浓度的松弛沟道区。 不是首先将锗引入通道，然后尝试松弛所得到的应变膜，最初形成松弛的通道以接受锗。 以这种方式，可以建立锗的存在而不会使晶格变形或损坏。 在将锗引入鳍状晶格结构之前，门结构相对于本征硅散热片图案化，以确保栅极正确对准。 在对齐栅极结构之后，将硅片段分段以弹性地松弛硅晶格。 然后，将锗引入松弛的硅晶格中，以产生基本上无应力且也无缺陷的SiGe沟道。 使用所述方法，在结构稳定的膜中实现的锗的浓度可以增加到大于85％的水平。

公开(公告)号：US20170005012A1

公开(公告)日：2017-01-05

申请号：US15238559

申请日：2016-08-16

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L21/84 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308 ,  H01L29/161 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L27/12 ,  H01L27/02

CPC classification number: H01L21/845 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3081 ,  H01L27/0207 ,  H01L27/1211 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/4236 ,  H01L29/66795

Abstract: An analog integrated circuit is disclosed in which short channel transistors are stacked on top of long channel transistors, vertically separated by an insulating layer. With such a design, it is possible to produce a high density, high power, and high performance analog integrated circuit chip including both short and long channel devices that are spaced far enough apart from one another to avoid crosstalk. In one embodiment, the transistors are FinFETs and the long channel devices are multi-gate FinFETs. In one embodiment, single and dual damascene devices are combined in a multi-layer integrated circuit cell. The cell may contain various combinations and configurations of the short and long-channel devices. A high density cell can be made by simply shrinking the dimensions of the cells and replicating two or more cells in the same size footprint as the original cell.

Abstract translation: 公开了一种模拟集成电路，其中短沟道晶体管堆叠在由绝缘层垂直分隔的长沟道晶体管的顶部。 通过这样的设计，可以生产高密度，高功率和高性能的模拟集成电路芯片，其包括彼此间隔足够远的短路和长通道设备，以避免串扰。 在一个实施例中，晶体管是FinFET，并且长沟道器件是多栅极FinFET。 在一个实施例中，将单镶嵌和双镶嵌装置组合在多层集成电路单元中。 小区可以包含短路和长通道设备的各种组合和配置。 可以通过简单地收缩细胞的尺寸并复制与原始细胞相同尺寸足迹的两个或更多个细胞来制造高密度细胞。

公开(公告)号：US09536756B1

公开(公告)日：2017-01-03

申请号：US14754143

申请日：2015-06-29

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo ,  Amor Zapanta

IPC: H01L21/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78

CPC classification number: H01L21/566 ,  H01L21/4825 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012

Abstract: One or more embodiments are directed to semiconductor packages that are assembled using a sacrificial material, that when removed, separates the assembled packages into individual packages. The sacrificial material may be removed by a blanket technique such that a mask, pattern, or alignment step is not needed. In one embodiment the sacrificial material is formed on the lead frame on a connecting bar of a lead frame between adjacent leads. After the molding step, the connecting bar is etched away exposing a surface of the sacrificial material. The sacrificial material is removed, thereby separating the assembled packages into individual packages.

Abstract translation: 一个或多个实施例涉及使用牺牲材料组装的半导体封装，当被移除时，将组装的封装分离成单个封装。 可以通过覆盖技术去除牺牲材料，使得不需要掩模，图案或对准步骤。 在一个实施例中，牺牲材料形成在引线框架上的相邻引线之间的引线框架的连接杆上。 在模制步骤之后，连接杆被蚀刻掉，暴露牺牲材料的表面。 去除牺牲材料，从而将组装的包装分离成单独的包装。

公开(公告)号：US20160379916A1

公开(公告)日：2016-12-29

申请号：US14753365

申请日：2015-06-29

Applicant: STMICROELECTRONICS, INC.

Inventor： Jefferson TALLEDO

IPC: H01L23/495 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78

CPC classification number: H01L24/85 ,  H01L21/4842 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49544 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00015

Abstract: A method is for making a semiconductor device. The method may include providing a lead frame having a recess, forming a sacrificial material in the recess of the lead frame, and mounting an IC on the lead frame. The method may include encapsulating the IC and the lead frame, removing portions of the lead frame to define lead frame contacts for the IC, and removing the sacrificial material to define for each lead frame contact a solder anchoring tab extending outwardly at a lower region and defining a sidewall recess between opposing portions of the solder anchoring tab and the encapsulation material.

Abstract translation: 一种制造半导体器件的方法。 该方法可以包括提供具有凹部的引线框架，在引线框架的凹部中形成牺牲材料，并将IC安装在引线框架上。 该方法可以包括封装IC和引线框架，去除引线框架的部分以限定用于IC的引线框架触点，并且移除牺牲材料以限定每个引线框架接触在较低区域向外延伸的焊料锚定片， 在焊料锚固片和包封材料的相对部分之间限定侧壁凹陷。

公开(公告)号：US20160379846A1

公开(公告)日：2016-12-29

申请号：US14754143

申请日：2015-06-29

Applicant: STMicroelectronics, Inc.

Inventor： Jefferson Talledo ,  Amor Zapanta

IPC: H01L21/56 ,  H01L21/78 ,  H01L21/48

CPC classification number: H01L21/566 ,  H01L21/4825 ,  H01L21/4832 ,  H01L21/561 ,  H01L21/78 ,  H01L23/3107 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012

Abstract: One or more embodiments are directed to semiconductor packages that are assembled using a sacrificial material, that when removed, separates the assembled packages into individual packages. The sacrificial material may be removed by a blanket technique such that a mask, pattern, or alignment step is not needed. In one embodiment the sacrificial material is formed on the lead frame on a connecting bar of a lead frame between adjacent leads. After the molding step, the connecting bar is etched away exposing a surface of the sacrificial material. The sacrificial material is removed, thereby separating the assembled packages into individual packages.

Abstract translation: 一个或多个实施例涉及使用牺牲材料组装的半导体封装，当被移除时，将组装的封装分离成单个封装。 可以通过覆盖技术去除牺牲材料，使得不需要掩模，图案或对准步骤。 在一个实施例中，牺牲材料形成在引线框架上的相邻引线之间的引线框架的连接杆上。 在模制步骤之后，连接杆被蚀刻掉，暴露牺牲材料的表面。 去除牺牲材料，从而将组装的包装分离成单独的包装。

公开(公告)号：US20160365309A1

公开(公告)日：2016-12-15

申请号：US14734013

申请日：2015-06-09

Applicant: STMicroelectronics, Inc.

Inventor： John Hongguang Zhang

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/768 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/535 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78696

Abstract: An integrated circuit includes a source-drain region, a channel region adjacent to the source-drain region, a gate structure extending over the channel region and a sidewall spacer on a side of the gate structure and which extends over the source-drain region. A dielectric layer is provided in contact with the sidewall spacer and having a top surface. The gate structure includes a gate electrode and a gate contact extending from the gate electrode as a projection to reach the top surface. The side surfaces of the gate electrode and a gate contact are aligned with each other. The gate dielectric layer for the transistor positioned between the gate electrode and the channel region extends between the gate electrode and the sidewall spacer and further extends between the gate contact and the sidewall spacer.

Abstract translation: 集成电路包括源极 - 漏极区域，与源极 - 漏极区域相邻的沟道区域，在沟道区域上延伸的栅极结构和在栅极结构侧面上的侧壁间隔物并且在源极 - 漏极区域上延伸。 提供与侧壁间隔物接触并具有顶表面的电介质层。 栅极结构包括栅极电极和从栅电极延伸的栅极接触，作为突起到达顶表面。 栅电极和栅极触点的侧表面彼此对准。 位于栅电极和沟道区之间的晶体管的栅极电介质层在栅电极和侧壁间隔物之间​​延伸，并且进一步在栅极接触件和侧壁间隔件之间延伸。