公开(公告)号：US20190027439A1

公开(公告)日：2019-01-24

申请号：US16037595

申请日：2018-07-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Julien DELALLEAU ,  Christian RIVERO

IPC: H01L23/535 ,  H01L29/78 ,  H01L23/528 ,  H01L29/66 ,  H01L21/28 ,  H01L21/768

Abstract: An integrated circuit includes a substrate and an interconnect. A substrate zone is delineated by an insulating zone. A polysilicon region extends on the insulating zone and includes a strip part. An isolating region is situated between the substrate and the interconnect and covers the substrate zone and the polysilicon region. A first electrically conductive pad passes through the isolating region and has a first end in electrical contact with both the strip part and the substrate zone. A second end of the electrically conductive pad is in electrical contact with the interconnect. A second electrically conductive pad also passes through the isolating region to make electrical contact with another region. The first and second electrically conductive pads have equal or substantially equal cross sectional sizes, within a tolerance.

公开(公告)号：US10162728B2

公开(公告)日：2018-12-25

申请号：US15222368

申请日：2016-07-28

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Albert Martinez

IPC: G06F11/00 ,  G06F11/36 ,  G06F9/30

Abstract: A method for monitoring the execution of a program code by a monitoring program code may include storing instructions of the program code and instructions for monitoring the program code in the same program memory. Each instruction to be monitored and the associated monitoring instructions may be simultaneously extracted from the program memory, and the instruction to be monitored and the monitoring instructions may be executed.

公开(公告)号：US10157720B2

公开(公告)日：2018-12-18

申请号：US14517369

申请日：2014-10-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio di-Giacomo ,  Brice Arrazat

IPC: H01H61/02 ,  H01H1/58 ,  H01H9/02 ,  B81B3/00

Abstract: A device includes a thermally deformable assembly accommodated in a cavity of the interconnection part of an integrated circuit. The assembly can bend when there is a variation in temperature, so that its free end zone is displaced vertically. The assembly can be formed in the back end of line of the integrated circuit.

公开(公告)号：US20180341788A1

公开(公告)日：2018-11-29

申请号：US15920835

申请日：2018-03-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Alexandre Sarafianos ,  Thomas Ordas

IPC: G06F21/76 ,  G11C19/28 ,  H03K19/003 ,  H03K19/21 ,  H03K19/20

Abstract: A device can be used for detecting faults. A shift register is suitable for shifting, in tempo with a clock, a binary signal alternating between two logic levels, in successive cells of the shift register. A first logic circuit is suitable for comparing values contained in at least one pair of cells of the register.

公开(公告)号：US20180330780A1

公开(公告)日：2018-11-15

申请号：US15978003

申请日：2018-05-11

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN ,  Simon JEANNOT ,  Olivier WEBER

IPC: G11C13/00 ,  H01L45/00

Abstract: The disclosure relates to a memory cell comprising a resistive RAM memory element and a selection transistor, in which the memory element is positioned on a flank of the selection transistor.

公开(公告)号：US20180330203A1

公开(公告)日：2018-11-15

申请号：US15924608

申请日：2018-03-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pierre Demaj ,  Laurent Folliot

IPC: G06K9/62 ,  G06K9/00

CPC classification number: G06K9/6282 ,  G06K9/00624 ,  G06K9/6277 ,  G06K9/6293

Abstract: A method is provided for monitoring scene detection by an apparatus detecting scenes from among a set of possible reference scenes. It includes an assignment of an identifier to each reference scene, detection of scenes from among the set of possible reference scenes at successive instants of detection with the aid of at least one classification algorithm, and a sliding time filtering processing of these detected current scenes over a filtering window of size M, based on the identifier of each new detected current scene taken into account in the window and a confidence probability associated with this new detected current scene, the output of the filtering processing successively delivering filtered detected scenes.

公开(公告)号：US20180329721A1

公开(公告)日：2018-11-15

申请号：US16026233

申请日：2018-07-03

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Nicolas Froidevaux ,  Jean-Michel Gril-Maffre ,  Jean-Pierre Leca

IPC: G06F9/4401 ,  H03K19/00 ,  G06F1/24 ,  G06F1/32 ,  G06F1/28

Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.

公开(公告)号：US20180321727A1

公开(公告)日：2018-11-08

申请号：US15883216

申请日：2018-01-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Bruno Gailhard

IPC: G06F1/28 ,  H02H3/24 ,  G01R19/165 ,  H03K5/08

CPC classification number: G06F1/28 ,  G01R19/16552 ,  H02H1/06 ,  H02H3/05 ,  H02H3/24 ,  H02H3/247 ,  H02M2001/0006 ,  H03K5/082

Abstract: An integrated processing unit is supplied by a power supply voltage present at the terminals of a capacitor configured to supply a maximum permissible voltage drop. A periodic pulse signal is generated having a period that is less than or equal to a current period determined from the maximum permissible voltage drop and a current consumption of the processing unit. The power supply voltage is compared with a threshold voltage at the pulse rate of the periodic pulse signal. A control signal generated from that comparison is delivered to the processing unit and has a first value when the power supply voltage is greater than or equal to the threshold voltage and a second value when the power supply voltage is less than the threshold voltage.

公开(公告)号：US20180294030A1

公开(公告)日：2018-10-11

申请号：US16010268

申请日：2018-06-15

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois Tailliet ,  Marc Battista

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C5/144 ,  G11C13/0069 ,  G11C16/10 ,  G11C16/14 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3418 ,  G11C29/12005

Abstract: A method of controlling a cycle for writing at least one data item to at least one memory slot of the electrically programmable and erasable read-only memory type disposed in an electronic circuit supplied by a supply voltage includes a controlled increase of the duration of the write cycle in the presence of a decrease in the supply voltage.

公开(公告)号：US20180275737A1

公开(公告)日：2018-09-27

申请号：US15989731

申请日：2018-05-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Jonathan Cottinet ,  Jean Claude Bini

IPC: G06F1/32 ,  H04W52/02 ,  G06F3/16 ,  G10L15/22

CPC classification number: G06F1/324 ,  G06F1/3287 ,  G06F3/167 ,  G10L15/22 ,  G10L15/28 ,  G10L2015/088 ,  H04W52/0229 ,  H04W52/0251 ,  H04W52/0293 ,  H04W76/28 ,  Y02D70/00 ,  Y02D70/26

Abstract: An electronic device includes an appended module coupled to a core having a standby state comprising a first power supply circuit, a first clock and a circuit that recognizes multiple vocal commands timed by the first clock. The appended module includes a second power supply circuit independent of the first power supply circuit, a second clock independent of the first clock and having a frequency lower than that of the first clock, digital unit timed by the second clock including a sound capture circuit that delivers a processed sound signal, and a processing unit configured in order, in the presence of a parameter of the processed sound signal greater than a threshold, to analyze the content of the processed sound signal and to deliver, when the content of the sound signal comprises a reference pattern, an activating signal to the core that can take it out of its standby state.