公开(公告)号：US11929124B2

公开(公告)日：2024-03-12

申请号：US17597004

申请日：2020-11-11

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Umberto Di Vincenzo

IPC: G11C7/00 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C29/52

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C29/52

Abstract: The present disclosure relates to a method for accessing memory cells comprising: applying an increasing read voltage with a first polarity to the plurality of memory cells; counting a number of switching memory cells in the plurality based on the applying the increasing read voltage; applying a first read voltage with the first polarity based on the number of switched memory cells reaching a threshold number; applying a second read voltage with a second polarity opposite to the first polarity; and determining that a memory cell in the plurality of memory cells has a first logic value based on the memory cell having switched during one of the applying the increasing read voltage and the applying the first read voltage or based on the memory cell not having switched during the applying the second read voltage. A related system is also disclosed.

公开(公告)号：US11887689B2

公开(公告)日：2024-01-30

申请号：US17585307

申请日：2022-01-26

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/12 ,  G11C11/22

CPC classification number: G11C7/12 ,  G11C11/221 ,  G11C11/2255 ,  G11C11/2273 ,  G11C11/2293

Abstract: Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency associated with accessing a memory device. During a read operation, the memory device may select a word line to couple the memory cell with a selected digit line. Further, the memory device may selectively couple the selected digit line with a reference digit line that is to be precharged to a given voltage. A difference in voltage between the selected digit line and the reference digit line at the completion of precharging may represent a signal indicative of a logic state of the memory cell. The memory device may use a capacitor precharged to a first voltage to capture the signal. In some cases, the memory device may continue to perform a self-reference operation using the same memory cell, the selected digit line, and the reference digit line to produce a reference signal using the capacitor precharged to a different voltage. A similar precharging steps may be repeated during the self-reference operation. The selected word line may remain activated during the read operation and the self-reference operation.

公开(公告)号：US11887663B2

公开(公告)日：2024-01-30

申请号：US18079494

申请日：2022-12-12

Applicant: Micron Technology, Inc.

Inventor： Graziano Mirichigni ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C11/22 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2013/0045

Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a first voltage at a first time duration to the memory array based on the read request. The control circuit is additionally configured to count a number of the plurality of memory cells that have switched to an active read state based on the first voltage and to derive a second time duration. The control circuit is further configured to apply a second voltage at the second duration to the memory array. The control circuit is also configured to return the data based at least on bits stored in a first and a second set of the plurality of memory cells.

公开(公告)号：US20240013831A1

公开(公告)日：2024-01-11

申请号：US17611253

申请日：2020-12-09

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: G11C11/4096 ,  G11C11/404

CPC classification number: G11C11/4096 ,  G11C11/4045

Abstract: The present disclosure describes a memory device comprising memory cells at cross points of access lines of a memory array, and a two-transistor driver comprising a P-type transistor and a N-type transistor connected to the P-type transistor, the two-transistor driver being configured to drive an access line of the memory array to a discharging voltage during an IDLE phase, to drive said access line to a floating voltage during an ACTIVE phase, and to drive said access line at least to a first or second read/program voltage during a PULSE phase.

公开(公告)号：US20230420025A1

公开(公告)日：2023-12-28

申请号：US17852221

申请日：2022-06-28

Applicant: Micron Technology, Inc.

Inventor： Umberto di Vincenzo ,  Ferdinando Bedeschi ,  Christian Marc Benoit Caillat

IPC: G11C11/406 ,  G11C11/4096 ,  G11C11/4074

CPC classification number: G11C11/40615 ,  G11C11/40622 ,  G11C11/4096 ,  G11C11/4074

Abstract: A system includes a memory array having pattern cells and data cells. The pattern cells are configured to store only a first logic state. The data cells are configured to store the first logic state or a second logic state. Bias circuitry is configured to apply voltages to the pattern cells and data cells. Sensing circuitry is configured to read the pattern cells. A controller is configured to apply, using the bias circuitry, first voltages to the pattern cells; determine, using the sensing circuitry, that at least a portion of the pattern cells switch; determine, based on the portion of the pattern cells that switch, to refresh a codeword; and apply, using the bias circuitry, the refresh of the codeword.

公开(公告)号：US20230393766A1

公开(公告)日：2023-12-07

申请号：US17823371

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0673 ,  G06F3/0629

Abstract: Methods, systems, and devices for transistor configurations for vertical memory arrays are described. A memory device may implement a multi-transistor architecture, such as a two-transistor architecture, that is operable to couple pillars with bit lines. For example, a memory device may include a conductive pillar that extends through levels of a memory array. The pillar may be coupled with a first bit line via a first transistor and coupled with a second bit line via a second transistor. To access a memory cell coupled with the pillar, the memory device may bias a word line coupled with the memory cell to a first access voltage, bias one of the bit lines to a second access voltage, activate one of the transistors to couple the pillar with the one of the bit lines, and deactivate the other transistor to isolate the pillar from the other of the bit lines.

公开(公告)号：US11810609B2

公开(公告)日：2023-11-07

申请号：US17563395

申请日：2021-12-28

Applicant: Micron Technology, Inc.

Inventor： Efrem Bolandrina ,  Ferdinando Bedeschi

IPC: G11C11/00 ,  G11C11/22

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2255 ,  G11C11/2257

Abstract: Techniques are described for maintaining a stable voltage difference in a memory device, for example, during a critical operation (e.g., a sense operation). The voltage difference to be maintained may be a read voltage across a memory cell or a difference associated with a reference voltage, among other examples. A component (e.g., a local capacitor) may be coupled, before the operation, with a node biased to a first voltage (e.g., a global reference voltage) to sample a voltage difference between the first voltage and a second voltage while the circuitry is relatively quiet (e.g., not noisy). The component may be decoupled from the node before the operation such that a node of the component (e.g., a capacitor) may be allowed to float during the operation. The voltage difference across the component may remain stable during variations in the second voltage and may provide a stable voltage difference during the operation.

公开(公告)号：US20230206977A1

公开(公告)日：2023-06-29

申请号：US18120133

申请日：2023-03-10

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Efrem Bolandrina

IPC: G11C11/22 ,  G06F13/16

CPC classification number: G11C11/2259 ,  G06F13/1694 ,  G11C11/221 ,  G11C11/2257 ,  G11C11/2255

Abstract: Methods, systems, and devices for a single plate configuration and memory array operation are described. A non-volatile memory array may utilize a single plate to cover a subset of the array. One or more memory cells of the subset may be selected by operating the plate and an access line of an unselected memory cell at a fixed voltage. A second voltage may be applied to an access line of the selected cell, and subsequently reduced to perform an access operation. Removing the applied voltage may allow for the memory cell to undergo a recovery period prior to a subsequent access operation.

公开(公告)号：US20230141713A1

公开(公告)日：2023-05-11

申请号：US16976690

申请日：2020-03-03

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto ,  Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C29/46 ,  G11C29/12 ,  G11C29/42

CPC classification number: G11C29/46 ,  G11C29/42 ,  G11C29/1201

Abstract: Methods, systems, and devices related to counter-based sense amplifier method for memory cells are described. The counter-based read algorithm may comprise the following phases:

storing in a counter associated to an array of memory cells the value of the number of bits having a predetermined logic value of the data bits stored in the memory array;
reading from said counter the value corresponding to the number of bits having the predetermined logic value;
reading the data stored in the array of memory cells by applying a ramp of biasing voltages;
counting the number of bits having the predetermined logic value during the data reading phase;
stopping the data reading phase when the number of bits having the predetermined logic value is equal to the value stored in said counter.

公开(公告)号：US20230039775A1

公开(公告)日：2023-02-09

申请号：US17969269

申请日：2022-10-19

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: G11C29/42 ,  G11C29/44 ,  G11C11/4091 ,  G11C29/02

Abstract: Apparatuses and methods for compensating for signal drop in memory. Compensating for signal drop can include applying a first signal to a terminal of a particular transistor and mirroring the first signal to a decoder replica. Compensating for signal drop can also include applying a second signal to a gate of the particular transistor, the second signal comprising a sensing signal and a signal drop on the decoder replica and sensing a state of the particular transistor.