公开(公告)号：US20120285517A1

公开(公告)日：2012-11-15

申请号：US13103490

申请日：2011-05-09

申请人： Joel P. de Souza ,  Harold John Hovel ,  Daniel Inns ,  Jeehwan Kim ,  Christian Lavoie ,  Conal Eugene Murray ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam Shahidi ,  Davood Shahrjerdi ,  Zhen Zhang

发明人： Joel P. de Souza ,  Harold John Hovel ,  Daniel Inns ,  Jeehwan Kim ,  Christian Lavoie ,  Conal Eugene Murray ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam Shahidi ,  Davood Shahrjerdi ,  Zhen Zhang

IPC分类号： H01L31/108 ,  H01L31/18

CPC分类号： H01L31/07 ,  H01L31/0321 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A Schottky Barrier solar cell having at least one of a low work function region and a high work function region provided on the front or back surface of a lightly-doped absorber material, which may be produced in a variety of different geometries. The method of producing the Schottky Barrier solar cells allows for short processing times and the use of low temperatures.

摘要翻译： 一种肖特基势垒太阳能电池，其具有设置在轻掺杂的吸收材料的前表面或后表面上的低功函数区域和高功函数区域中的至少一个，其可以以各种不同的几何形状生产。 生产肖特基势垒太阳能电池的方法允许短的处理时间和低温的使用。

公开(公告)号：US20120252216A1

公开(公告)日：2012-10-04

申请号：US13075657

申请日：2011-03-30

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Alexander Reznicek ,  Devendra K. Sadana

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Alexander Reznicek ,  Devendra K. Sadana

IPC分类号： H01L21/302

CPC分类号： H01L21/02046

摘要： Low-temperature in-situ techniques are provided for the removal of oxide from a silicon surface during CMOS epitaxial processing. Oxide is removed from a semiconductor wafer having a silicon surface, by depositing a SiGe layer on the silicon surface; etching the SiGe layer from the silicon surface at a temperature below 700 C (and above, for example, approximately 450 C); and repeating the depositing and etching steps a number of times until a contaminant is substantially removed from the silicon surface. In one variation, the deposited layer comprises a group IV semiconductor material and/or an alloy thereof.

摘要翻译： 提供低温原位技术用于在CMOS外延处理期间从硅表面去除氧化物。 通过在硅表面上沉积SiGe层，从具有硅表面的半导体晶片去除氧化物; 在低于700℃（以上，例如约450℃）的温度下，从硅表面蚀刻SiGe层; 并重复沉积和蚀刻步骤多次，直到污染物基本上从硅表面除去。 在一个变型中，沉积层包括IV族半导体材料和/或其合金。

公开(公告)号：US20120216862A1

公开(公告)日：2012-08-30

申请号：US13036584

申请日：2011-02-28

申请人： Ahmed Abou-Kandil ,  Nasser Afify ,  Wanda Andreoni ,  Alessandro Curioni ,  Augustin J. Hong ,  Jeehwan Kim ,  Petr Khomyakov ,  Devendra K. Sadana

发明人： Ahmed Abou-Kandil ,  Nasser Afify ,  Wanda Andreoni ,  Alessandro Curioni ,  Augustin J. Hong ,  Jeehwan Kim ,  Petr Khomyakov ,  Devendra K. Sadana

IPC分类号： H01L31/0264 ,  H01L31/0376 ,  H01L31/20

CPC分类号： H01L31/202 ,  C23C16/24 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02658 ,  H01L31/0376 ,  H01L31/03926 ,  H01L31/075 ,  Y02E10/548 ,  Y02P70/521

摘要： A method of producing a photovoltaic device includes providing a stretchable substrate for the photovoltaic device; and stretching the substrate to produce a stretched substrate. The method further includes depositing a structure comprising hydrogenated amorphous silicon onto the stretched substrate; and subjecting the deposited hydrogenated amorphous silicon structure and the stretched substrate to a compressive force to form a compressively strained photovoltaic device.

摘要翻译： 制造光伏器件的方法包括提供用于光伏器件的可拉伸衬底; 并拉伸基底以产生拉伸的基底。 该方法还包括将包含氢化非晶硅的结构沉积在拉伸的基底上; 以及对沉积的氢化非晶硅结构和拉伸的基底进行压缩力以形成压缩应变光伏器件。

公开(公告)号：US20120190161A1

公开(公告)日：2012-07-26

申请号：US13437036

申请日：2012-04-02

申请人： Jee Hwan Kim ,  Stephen W. Bedell ,  Siegfried Maurer ,  Devendra K. Sadana

发明人： Jee Hwan Kim ,  Stephen W. Bedell ,  Siegfried Maurer ,  Devendra K. Sadana

IPC分类号： H01L21/336

CPC分类号： H01L21/26513 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66636 ,  Y10S438/919

摘要： A field effect transistor (FET) has a channel hosted in Ge. The FET has silicon-germanium (SiGe) source and drain formed by selective epitaxy. The SiGe source and drain exert a tensile stress onto the Ge channel. During forming of the SiGe source and drain, an n-type dopant species and a compensating species are being incorporated into the SiGe source and drain. The n-type dopant species and the compensating species are so selected that the size of the SiGe atomic radius is inbetween the dopant atomic radius and the compensating species atomic radius.

摘要翻译： 场效应晶体管（FET）具有在Ge中托管的通道。 FET通过选择性外延形成硅 - 锗（SiGe）源极和漏极。 SiGe源极和漏极在Ge沟道上施加拉伸应力。 在形成SiGe源极和漏极期间，n型掺杂物质和补偿物质被并入到SiGe源极和漏极中。 选择n型掺杂物种类和补偿种类，使得SiGe原子半径的尺寸在掺杂剂原子半径和补偿物质原子半径之间。

公开(公告)号：US20120152352A1

公开(公告)日：2012-06-21

申请号：US12968490

申请日：2010-12-15

申请人： Tze-Chiang Chen ,  Jee H. Kim ,  Devendra K. Sadana ,  Ahmed Abou-Kandil ,  Mohamed Saad

发明人： Tze-Chiang Chen ,  Jee H. Kim ,  Devendra K. Sadana ,  Ahmed Abou-Kandil ,  Mohamed Saad

IPC分类号： H01L31/0264 ,  H01L31/18

CPC分类号： H01L31/075 ,  H01L31/02167 ,  H01L31/1816 ,  Y02E10/548

摘要： A germanium-containing layer is provided between a p-doped silicon-containing layer and a transparent conductive material layer of a photovoltaic device. The germanium-containing layer can be a p-doped silicon-germanium alloy layer or a germanium layer. The germanium-containing layer has a greater atomic concentration of germanium than the p-doped silicon-containing layer. The presence of the germanium-containing layer has the effect of reducing the series resistance and increasing the shunt resistance of the photovoltaic device, thereby increasing the fill factor and the efficiency of the photovoltaic device. In case a silicon-germanium alloy layer is employed, the closed circuit current density also increases.

摘要翻译： 在p掺杂的含硅层和光伏器件的透明导电材料层之间提供含锗层。 含锗层可以是p掺杂的硅 - 锗合金层或锗层。 含锗层具有比p掺杂的含硅层更大的锗原子浓度。 含锗层的存在具有降低串联电阻并增加光伏器件的分流电阻的效果，从而增加光伏器件的填充因子和效率。 在使用硅 - 锗合金层的情况下，闭路电流密度也增加。

公开(公告)号：US08169025B2

公开(公告)日：2012-05-01

申请号：US12689339

申请日：2010-01-19

申请人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Stephen W. Bedell ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/7849

摘要： A semiconductor device and fabrication method include a strained semiconductor layer having a strain in one axis. A long fin and a short fin are formed in the semiconductor layer such that the long fin has a strained length along the one axis. An n-type transistor is formed on the long fin, and a p-type transistor is formed on the at least one short fin. The strain in the n-type transistor improves performance.

摘要翻译： 半导体器件和制造方法包括在一个轴上具有应变的应变半导体层。 在半导体层中形成长鳍片和短鳍片，使得长鳍片沿着一个轴线具有应变长度。 在长鳍片上形成n型晶体管，在该至少一个短鳍片上形成p型晶体管。 n型晶体管中的应变提高了性能。

公开(公告)号：US08138061B2

公开(公告)日：2012-03-20

申请号：US11031165

申请日：2005-01-07

申请人： Joel P. de Souza ,  John A. Ott ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger

发明人： Joel P. de Souza ,  John A. Ott ,  Alexander Reznicek ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC分类号： H01L21/46

CPC分类号： H01L21/187 ,  H01L21/76251

摘要： The present invention provides a method for removing or reducing the thickness of ultrathin interfacial oxides remaining at Si—Si interfaces after silicon wafer bonding. In particular, the invention provides a method for removing ultrathin interfacial oxides remaining after hydrophilic Si—Si wafer bonding to create bonded Si—Si interfaces having properties comparable to those achieved with hydrophobic bonding. Interfacial oxide layers of order of about 2 to about 3 nm are dissolved away by high temperature annealing, for example, an anneal at 1300°-1330° C. for 1-5 hours. The inventive method is used to best advantage when the Si surfaces at the bonded interface have different surface orientations, for example, when a Si surface having a (100) orientation is bonded to a Si surface having a (110) orientation. In a more general aspect of the invention, the similar annealing processes may be used to remove undesired material disposed at a bonded interface of two silicon-containing semiconductor materials. The two silicon-containing semiconductor materials may be the same or different in surface crystal orientation, microstructure (single-crystal, polycrystalline, or amorphous), and composition.

摘要翻译： 本发明提供一种在硅晶片接合之后去除或减少残留在Si-Si界面处的超薄界面氧化物的厚度的方法。 特别地，本发明提供了一种去除在亲水性Si-Si晶片接合之后残留的超薄界面氧化物以产生具有与用疏水性接合实现的特性相当的性质的结合Si-Si界面的方法。 约2至约3nm的界面氧化物层通过高温退火（例如1300°-1330℃退火1-5小时）被溶解掉。 当粘合界面处的Si表面具有不同的表面取向时，例如当具有（100）取向的Si表面被结合到具有（110）取向的Si表面时，本发明的方法被用于最好的优点。 在本发明的更一般的方面中，类似的退火工艺可用于去除设置在两个含硅半导体材料的键合界面处的不期望的材料。 两种含硅半导体材料在表面晶体取向，微结构（单晶，多晶或无定形）和组成上可以相同或不同。

公开(公告)号：US08128749B2

公开(公告)日：2012-03-06

申请号：US11867235

申请日：2007-10-04

申请人： Junedong Lee ,  Devendra K. Sadana ,  Dominic J. Schepis

发明人： Junedong Lee ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC分类号： C30B21/02

CPC分类号： H01L21/76243 ,  H01L21/3226 ,  H01L21/76254 ,  H01L29/78603

摘要： An SOI substrate has a gettering layer of silicon-germanium (SiGe) with 5-10% Ge, and a thickness of approximately 50-1000 nm. Carbon (C) may be added to SiGe to stabilize the dislocation network. The SOI substrate may be a SIMOX SOI substrate, or a bonded SOI substrate, or a seeded SOI substrate. The gettering layer may disposed under a buried oxide (BOX) layer. The gettering layer may be disposed on a backside of the substrate.

摘要翻译： SOI衬底具有具有5-10％Ge的硅 - 锗（SiGe）吸收层，并且厚度约为50-1000nm。 碳（C）可以添加到SiGe中以稳定位错网络。 SOI衬底可以是SIMOX SOI衬底，或者键合的SOI衬底或者是接种的SOI衬底。 吸气层可以设置在掩埋氧化物（BOX）层下面。 吸气层可以设置在衬底的背面。

公开(公告)号：US20120012167A1

公开(公告)日：2012-01-19

申请号：US12835238

申请日：2010-07-13

申请人： Ahmed Abou-Kandil ,  Keith E. Fogel ,  Jee H. Kim ,  Mohamed Saad ,  Devendra K. Sadana

发明人： Ahmed Abou-Kandil ,  Keith E. Fogel ,  Jee H. Kim ,  Mohamed Saad ,  Devendra K. Sadana

IPC分类号： H01L31/0288 ,  H01L31/18

CPC分类号： H01L31/075 ,  H01L31/022466 ,  H01L31/03685 ,  H01L31/03687 ,  H01L31/03762 ,  H01L31/03921 ,  H01L31/1816 ,  H01L31/1824 ,  Y02E10/545 ,  Y02E10/548 ,  Y02P70/521

摘要： A p-doped semiconductor layer of a photovoltaic device is formed employing an inert gas within a carrier gas. The presence of the inert gas within the carrier gas increases free hole density within the p-doped semiconductor layer. This decreases the Schottky barrier at an interface with a transparent conductive material layer, thereby significantly reducing the series resistance of the photovoltaic device. The reduction of the series resistance increases the open-circuit voltage, the fill factor, and the efficiency of the photovoltaic device. This effect is more prominent if the p-doped semiconductor layer is also doped with carbon, and has a band gap greater than 1.85V. The p-doped semiconductor material of the p-doped semiconductor layer can be hydrogenated if the carrier gas includes a mix of H2 and the inert gas.

摘要翻译： 使用载气内的惰性气体形成光伏器件的p掺杂半导体层。 载气内的惰性气体的存在增加了p掺杂半导体层内的自由空穴密度。 这降低了在与透明导电材料层的界面处的肖特基势垒，从而显着降低了光伏器件的串联电阻。 串联电阻的降低增加了光伏器件的开路电压，填充因子和效率。 如果p掺杂半导体层也掺杂有碳，并且具有大于1.85V的带隙，则该效果更加突出。 如果载气包括H 2和惰性气体的混合物，则p掺杂半导体层的p掺杂半导体材料可以被氢化。

公开(公告)号：US20120009766A1

公开(公告)日：2012-01-12

申请号：US12830626

申请日：2010-07-06

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/20

CPC分类号： H01L29/1054 ,  H01L29/7833

摘要： A method of forming a strained semiconductor-on-insulator (SSOI) substrate that does not include wafer bonding is provided. In this disclosure a relaxed and doped silicon layer is formed on an upper surface of a silicon-on-insulator (SOI) substrate. In one embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is smaller than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is smaller than the in-plane lattice parameter of the underlying SOI layer. In another embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is larger than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is larger than the in-plane lattice parameter of the underlying SOI layer. After forming the relaxed and doped silicon layer on the SOI substrate, the dopant within the relaxed and doped silicon layer is removed from that layer converting the relaxed and doped silicon layer into a strained (compressively or tensilely) silicon layer that is formed on an upper surface of an SOI substrate.

摘要翻译： 提供了一种形成不包括晶片接合的应变绝缘体上半导体（SSOI）衬底的方法。 在本公开中，在绝缘体上硅（SOI）衬底的上表面上形成松弛和掺杂的硅层。 在一个实施例中，松弛和掺杂硅层内的掺杂剂具有小于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数小于硅的原子尺寸， 下层SOI层的平面晶格参数。 在另一实施例中，松弛和掺杂硅层内的掺杂剂具有大于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数大于硅原子尺寸， 下层SOI层的平面晶格参数。 在SOI衬底上形成松弛和掺杂的硅层之后，从该层去除松弛和掺杂硅层内的掺杂剂，将松散和掺杂的硅层转化成形成在上层的应变（压缩或拉伸）硅层 SOI衬底的表面。