公开(公告)号：US20240047229A1

公开(公告)日：2024-02-08

申请号：US17879110

申请日：2022-08-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SRI RANGA SAI BOYAPATI ,  RAJA SWAMINATHAN ,  DEEPAK VASANT KULKARNI

IPC: H01L21/48 ,  H01L23/498

CPC classification number: H01L21/486 ,  H01L23/49822 ,  H01L21/4857 ,  H01L23/49838 ,  H01L23/49894 ,  H01L21/6835

Abstract: A method for forming a core for a substrate that removes portions of a resist layer based on a pattern specifying widths of removed portions of the resist layer. The method forms a set of pillars by plating the remaining portions of the resist layer with a conductive material, so each pillar of the set has a perimeter plated with the conductive material. Additionally, each pillar of the set of pillars is encapsulated with a dielectric material. In some implementations, the dielectric material is an organic material.

公开(公告)号：US20240046418A1

公开(公告)日：2024-02-08

申请号：US17879473

申请日：2022-08-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Xiaodong Liang

IPC: G06T5/50 ,  H04N9/67 ,  H04N9/64 ,  G06T5/00 ,  G06T5/20

CPC classification number: G06T5/50 ,  H04N9/67 ,  H04N9/646 ,  G06T5/002 ,  G06T5/20 ,  G06T2207/10024 ,  G06T2207/10016

Abstract: Systems, apparatuses, and methods for implementing defogging techniques for images and video are disclosed. A defogging engine generates a defog filter result from a grayscale format version of an input image. An estimation engine generates an enhancement strength variable from a hue-saturation-value (HSV) format version of the input image. An enhancement engine receives both the defog filter result from the defogging engine and the enhancement strength variable from the estimation engine. The enhancement engine also receives the original red-green-blue (RGB) color space format version of the input image. The enhancement engine generates an enhanced version of the input image from the original RGB format version based on the defog filter result and the enhancement strength variable. The enhanced version of the input image mitigates fog, haze, mist or other environmental impediments that obscured the original input image.

公开(公告)号：US20240045456A1

公开(公告)日：2024-02-08

申请号：US17883216

申请日：2022-08-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Onn Lim Yong ,  Luca Ravezzi ,  Naman Parashar ,  Jeremy Zaks Walker

IPC: G05F1/575

CPC classification number: G05F1/575

Abstract: A method for regulating a supply voltage includes generating an output voltage on an output power supply node based on an input voltage on an input power supply node and a control signal on a control node of a common drain amplifier. The method includes generating the control signal using a mirrored current generated based on the input voltage. The mirrored current may be generated using a noise-compensating capacitor having a capacitance CNC, thereby compensating for a noise current generated by a parasitic gate-to-drain capacitance of the common drain amplifier based on the input voltage. The capacitance CNC may be approximately equal to 1/N times a parasitic gate-to-drain capacitance of the common drain amplifier, where N is greater than one. The current may be further based on a difference between a reference voltage and the output voltage on the output power supply node.

公开(公告)号：US20240038596A1

公开(公告)日：2024-02-01

申请号：US17873591

申请日：2022-07-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Chandra Sekhar Mandalapu ,  Rahul Agarwal ,  Rajasekaran Swaminathan ,  Richard T. Schultz

IPC: H01L21/84 ,  H01L21/02 ,  H01L23/14 ,  H01L23/498 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L21/02164 ,  H01L23/147 ,  H01L23/49827 ,  H01L27/1203

Abstract: An apparatus and method for efficiently increasing semiconductor chip functionality in a particular area. A semiconductor fabrication process (or process) grows a silicon substrate layer, and forms multiple p-type and n-type transistors along a front side surface of the silicon substrate layer. The process flips the silicon substrate layer and removes silicon substrate leaving a particular thickness of the silicon substrate layer. The process forms multiple p-type and n-type transistors along the back side surface of the silicon substrate layer, and forms metal layers that connect terminals of the transistors formed along the back side surface to particular signals. The process forms through silicon vias (TSVs) that traverse through the silicon substrate layer. The process again flips the silicon substrate layer, and forms metal layers that connect terminals of the transistors formed along the front side surface to particular signals.

公开(公告)号：US20240037312A1

公开(公告)日：2024-02-01

申请号：US18087025

申请日：2022-12-22

Applicant: ATI TECHNOLOGIES ULC ,  ADVANCED MICRO DEVICES, INC.

Inventor： David Akselrod ,  Tassanee Payakapan ,  Arie Margulis ,  Chad Robinson

IPC: G06F30/398

CPC classification number: G06F30/398

Abstract: Techniques for implementing selective scan insertion and verification that reduce production and verification time by enabling a test harness to insert and test scan chains are disclosed. Circuit nodes in a system model are selected and scan insertion is provided at the selected nodes. Selective scan insertion can be performed quickly and, in some implementations, automatedly to enable verification of correspondence of different system models or one or more system models and fabricated circuits. A request for manufacture may be generated including aspects of the system model to enable verification of a fabricated circuit in a similar or identical manner to those used to verify the system model.

公开(公告)号：US11886878B2

公开(公告)日：2024-01-30

申请号：US16712891

申请日：2019-12-12

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Sukesh Shenoy ,  Adam N. C. Clark ,  Indrani Paul

IPC: G06F1/00 ,  G06F9/30 ,  G06F9/48 ,  G06F1/3203 ,  G06F9/38

CPC classification number: G06F9/30083 ,  G06F1/3203 ,  G06F9/3877 ,  G06F9/4843 ,  G06F2009/3883

Abstract: An integrated coprocessor such as an accelerated processing unit (APU) generates commands for execution on a discrete coprocessor such as a discrete graphics processing unit (dGPU). Power distribution circuitry selectively provides power to the APU and the dGPU based on characteristics of workloads executing on the APU and the dGPU and based on a platform power limit that is shared by the APU and the dGPU. In some cases, the power distribution circuitry determines a first power provided to the APU and a second power provided to the dGPU. The power distribution circuitry increases the second power provided to the dGPU in response to a sum of the first and second powers being less than the platform power limit. In some cases, the power distribution circuitry modifies the power provided to the APU, the dGPU, or both in response to changes in temperatures measured by a set of sensors.

公开(公告)号：US20240027525A1

公开(公告)日：2024-01-25

申请号：US18364568

申请日：2023-08-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： AHMET TOKUZ ,  SAURABH B. UPADHYAY

IPC: G01R31/3185 ,  G01R31/3177 ,  G06F11/22

CPC classification number: G01R31/318583 ,  G01R31/3177 ,  G01R31/318572 ,  G06F11/2236

Abstract: A system for performing a scan test of a processor core includes a scan test module and a processor including a processor core and an input/output die, where the input/output die is coupled to the processor core. The scan test module transmits, in parallel to the input/output die, scan test input data. A serializer/deserializer module of the input/output die receives the input data, serializes the input data, and transmits the serialized input data to the processor core. A serializer/deserializer module of the processor core receives the serialized scan test input data, deserializes the input data, receives result data generated in dependence upon the input data, serializes the result data, and transmits the serialized result data to the input/output die. The input/output die serializer/deserializer module receives the result data, deserializes the result data, and provides the result data to the scan test module. Error detection can be carried out through redundancy.

公开(公告)号：US11880248B2

公开(公告)日：2024-01-23

申请号：US17486430

申请日：2021-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Christopher M. Jaggers ,  Christopher M. Helberg

IPC: G06F1/20 ,  G06F1/16 ,  H05K7/20

CPC classification number: G06F1/203 ,  G06F1/1632 ,  G06F2200/201 ,  H05K7/20254

Abstract: A docking station for secondary external cooling for mobile computing devices, including: one or more ports for docking a mobile computing device; a docking platform for supporting the mobile computing device; a cooling element; and a thermal interface housed in the docking platform for transferring heat between the mobile computing device and the cooling element.

公开(公告)号：US11876718B2

公开(公告)日：2024-01-16

申请号：US17961508

申请日：2022-10-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Narendra Kamat

IPC: H04L47/127 ,  H04L43/067 ,  H04L43/0876 ,  H04L43/16 ,  H04L47/10 ,  H04L47/30

CPC classification number: H04L47/127 ,  H04L43/067 ,  H04L43/0876 ,  H04L43/16 ,  H04L47/29 ,  H04L47/30

Abstract: Graded throttling for network-on-chip traffic, including: calculating, by an agent of a network-on-chip, a number of outstanding transactions issued by the agent; determining that the number of outstanding transactions meets a threshold; and implementing, by the agent, in response to the number of outstanding transactions meeting the threshold, a traffic throttling policy.

公开(公告)号：US11874739B2

公开(公告)日：2024-01-16

申请号：US17033398

申请日：2020-09-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Sudhanva Gurumurthi ,  Vilas Sridharan ,  Shaizeen Aga ,  Nuwan Jayasena ,  Michael Ignatowski ,  Shrikanth Ganapathy ,  John Kalamatianos

IPC: G06F11/10 ,  G06F21/60 ,  H04L9/32

CPC classification number: G06F11/1076 ,  G06F21/602 ,  H04L9/32

Abstract: A memory module includes one or more programmable ECC engines that may be programed by a host processing element with a particular ECC implementation. As used herein, the term “ECC implementation” refers to ECC functionality for performing error detection and subsequent processing, for example using the results of the error detection to perform error correction and to encode corrupted data that cannot be corrected, etc. The approach allows an SoC designer or company to program and reprogram ECC engines in memory modules in a secure manner without having to disclose the particular ECC implementations used by the ECC engines to memory vendors or third parties.