公开(公告)号：US5680362A

公开(公告)日：1997-10-21

申请号：US657637

申请日：1996-05-30

申请人： Michael C. Parris ,  Douglas B. Butler ,  Kim C. Hardee

发明人： Michael C. Parris ,  Douglas B. Butler ,  Kim C. Hardee

IPC分类号： G11C11/413 ,  G11C8/12 ,  G11C11/401 ,  G11C11/407 ,  G11C29/00 ,  G11C29/06 ,  G11C29/34 ,  G11C29/46 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C29/46 ,  G11C29/34 ,  G11C8/12

摘要： A circuit and method for concurrently addressing at least two rows of memory cells of a memory array of a memory device. By concurrently addressing at least two rows of memory cells during testing of the memory device during a burn-in period, the memory device can be tested in a reduced time period.

摘要翻译： 一种用于同时寻址存储器件的存储器阵列的至少两行存储器单元的电路和方法。 通过在老化期间在存储器件测试期间同时寻址至少两行存储器单元，可以在缩短的时间周期内对存储器件进行测试。

公开(公告)号：US5641697A

公开(公告)日：1997-06-24

申请号：US644447

申请日：1996-05-13

申请人： Eiichi Iwanami

发明人： Eiichi Iwanami

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L27/146 ,  H01L31/0232 ,  H01L21/265

CPC分类号： H01L27/14643 ,  H01L27/0251 ,  H01L27/0266 ,  H01L31/0232

摘要： A p-type high concentration doped region is formed in a p-type semiconductor substrate between a n-type doped region as part of an input protection circuit and another n-type doped region as part of internal circuitry. A plate is divided into two over the high concentration doped region. The high concentration doped region suppresses generation of a parasitic MOS transistor with the plate for a gate, one of the n-type doped regions for a source, and the other for a drain.

摘要翻译： 作为输入保护电路的一部分的n型掺杂区域和作为内部电路的一部分的另一个n型掺杂区域，在p型半导体衬底中形成p型高浓度掺杂区域。 在高浓度掺杂区域上将板分成两部分。 高浓度掺杂区域抑制寄生MOS晶体管的产生，栅极用栅极，用于源极的n型掺杂区域中的一个，漏极的另一个。

公开(公告)号：US5557135A

公开(公告)日：1996-09-17

申请号：US259158

申请日：1994-06-13

申请人： Masayuki Hashimoto

发明人： Masayuki Hashimoto

IPC分类号： H01L21/76 ,  H01L21/765 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/00

CPC分类号： H01L21/765 ,  H01L29/402

摘要： To electrically isolate a MOSFET formed on a substrate from an electrical device, a field shield electrode is buried in a substrate between the MOSFET and the electrical device so that the bottom surface of the field shield electrode is at a level deeper than each of depth levels of diffusion layers of the MOSFET and the electric device. To provide such an electrode, a trench is formed in a substrate at a level deeper than the depth levels of the diffusion layers of both the MOSFET and the electric device. After insulating an entire inner surface of the trench, an field shield electrode is buried and exposed surface of the electrode is covered with an insulating film.

摘要翻译： 为了将形成在衬底上的MOSFET与电气器件电隔离，场屏蔽电极被掩埋在MOSFET和电气器件之间的衬底中，使得场屏蔽电极的底表面比每个深度级更深 的MOSFET和电子器件的扩散层。 为了提供这种电极，在衬底中形成的沟槽的深度比MOSFET和电子器件的扩散层的深度级深。 在沟槽的整个内表面绝缘之后，掩埋场屏蔽电极，并且用绝缘膜覆盖电极的暴露表面。

公开(公告)号：US5532618A

公开(公告)日：1996-07-02

申请号：US983328

申请日：1992-11-30

申请人： Kim C. Hardee ,  Michael V. Cordoba

发明人： Kim C. Hardee ,  Michael V. Cordoba

IPC分类号： G01R31/26 ,  G01R31/28 ,  G05F1/46 ,  G11C11/401 ,  G11C11/407 ,  G11C11/413 ,  G11C29/00 ,  G11C29/06 ,  H03K17/00

CPC分类号： G05F1/465

摘要： A stress mode circuit is provided to generate a voltage that is either equal to a reference voltage or is a proportion of an external voltage (VCCEXT). The circuit includes two voltage divider circuits to provide the proportion voltage. Two differential amplifiers are provided to generate outputs corresponding to a comparison to the proportion voltage and the reference voltage. The outputs operate switches that couple the reference voltage or the proportion voltage to an output terminal.

摘要翻译： 提供应力模式电路以产生等于参考电压的电压或者是外部电压（VCCEXT）的比例。 该电路包括两个分压电路，以提供比例电压。 提供两个差分放大器以产生对应于比例电压和参考电压的比较的输出。 输出操作将参考电压或比例电压耦合到输出端子的开关。

公开(公告)号：US5347172A

公开(公告)日：1994-09-13

申请号：US964912

申请日：1992-10-22

申请人： Michael V. Cordoba ,  Kim C. Hardee

发明人： Michael V. Cordoba ,  Kim C. Hardee

IPC分类号： H02M3/07 ,  G05F1/46 ,  G05F3/20 ,  G11C5/14 ,  H01L21/822 ,  H01L27/04 ,  H03K19/096 ,  H03K3/354

CPC分类号： G05F1/465 ,  G05F3/205 ,  G11C5/14 ,  G11C5/145 ,  G11C5/146 ,  G11C5/147

摘要： A substrate bias generator avoids using a free-running oscillator and thereby saves power in the standby mode. A clock enable signal from a regulator sets a latch in a self-timed clock circuit. The latch setting initiates a first group of clock signals (that are used by a pump circuit for pumping), at the end of which the latch is reset but concomitantly an input circuit to the latch is disabled from recognizing a new pump signal. Resetting the latch causes the clock circuit to generate a second group of clock signals used in the charge pump to prepare fully for the next demand for pumping. At the end of the second group of clock signals, a full cycle of clocks has been completed in a self-timed manner, and the input circuit to the latch is reenabled to recognize a subsequent pump signal.

摘要翻译： 衬底偏置发生器避免使用自由运行的振荡器，从而在待机模式下节省功率。 来自稳压器的时钟使能信号在自定时钟电路中设置锁存器。 锁定设置启动第一组时钟信号（由泵浦电路用于泵浦），其中锁存器被复位，但伴随着锁存器的输入电路被禁止识别新的泵浦信号。 复位锁存器使得时钟电路产生在电荷泵中使用的第二组时钟信号，以充分满足下一个泵送需求。 在第二组时钟信号结束时，以自定时的方式完成了整个周期的时钟，并且重新使能到锁存器的输入电路以识别随后的泵浦信号。

公开(公告)号：US5347171A

公开(公告)日：1994-09-13

申请号：US961439

申请日：1992-10-15

申请人： Michael V. Cordoba ,  Kim C. Hardee

发明人： Michael V. Cordoba ,  Kim C. Hardee

IPC分类号： G05F3/20 ,  H02M3/07 ,  G05F1/56

CPC分类号： H02M3/073 ,  G05F3/205

摘要： A negative charge pump circuit for low voltage and wide voltage range applications. The charge pump includes two single-stage p-type pumps. One of the pumps is used to charge a circuit node down to a threshold voltage .vertline.Vt.sub.p .vertline. less than a desired voltage. When used in such a way, the other pump will charge a substrate to a full -VCC.

摘要翻译： 用于低电压和宽电压范围应用的负电荷泵电路。 电荷泵包括两个单级p型泵。 其中一个泵用于将电路节点充电到阈值电压| Vtp | 小于期望的电压。 当以这种方式使用时，另一个泵将对基板充电至完全-VCC。

公开(公告)号：US6087213A

公开(公告)日：2000-07-11

申请号：US094663

申请日：1998-06-15

申请人： Ichiro Murai ,  Hidemi Arakawa ,  Shinobu Shigeta

发明人： Ichiro Murai ,  Hidemi Arakawa ,  Shinobu Shigeta

IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L27/10852

摘要： A method of making a semiconductor memory device is discussed, which has a long refresh time and offers high reliability by minimizing junction leakage current, resulting in increased charge retention time. This is achieved by optimizing the diffusion layer junction depth formed in a deeper region of the semiconductor substrate which is in electrical contact with the impurity diffusion layer. Typically, junction depth is in excess of 0.1 .mu.m. Two methods for achieving such a structure are also provided. In one method, implantation voltage in excess of 80 KeV is used to implant P ions to form a high carrier concentration profile at a junction depth of greater than 0.1 .mu.m. In another method, implantation process are carried out in two steps so as to force the previously implanted ions deeper into the storage node electrode, and a subsequent heat treatment is carried out to further distribute the dopant ions into the substrate of the semiconductor substrate so as to disperse crystal defects into the substrate. The resulting structure is essentially free of crystal defects which cause current leakage from the boundary region between the dopant diffusion layer and the substrate in the conventional memory cell structure.

摘要翻译： 讨论了制造半导体存储器件的方法，其具有长的刷新时间，并且通过最小化结漏电流提供高可靠性，导致增加的电荷保持时间。 这通过优化在与杂质扩散层电接触的半导体衬底的较深区域中形成的扩散层结深而实现。 通常，结深度超过0.1μm。 还提供了用于实现这种结构的两种方法。 在一种方法中，使用超过80keV的注入电压来注入P离子，以在大于0.1μm的结深处形成高载流子浓度分布。 在另一种方法中，以两个步骤进行注入工艺，以便将先前注入的离子强制进入存储节点电极中，并进行随后的热处理，以进一步将掺杂剂离子分布到半导体衬底的衬底中，以便 以将晶体缺陷分散到衬底中。 所得到的结构基本上没有晶体缺陷，这些缺陷在常规的存储单元结构中引起了掺杂剂扩散层和衬底之间的边界区域的电流泄漏。

公开(公告)号：US6031407A

公开(公告)日：2000-02-29

申请号：US271477

申请日：1994-07-07

申请人： Michael V. Cordoba ,  Kim C. Hardee

发明人： Michael V. Cordoba ,  Kim C. Hardee

IPC分类号： H03K3/354 ,  H03K3/011 ,  H03K3/03 ,  H03K5/13 ,  H03K17/687

CPC分类号： H03K3/0315 ,  H03K3/011

摘要： A constant current source is used to provide a constant current to set a delay which defines the period of the output of the oscillator. The delay is preferably set by charging a capacitor with the constant current. Because the current is independent of variations in V.sub.CC and temperature, the capacitor will charge for a given period. Therefore, the frequency or period of oscillation will also be fixed and independent of variation in V.sub.CC or temperature. A current limiting circuit and latch are provided to generate an output which will be transmitted through one or a series of inverters. In an alternate embodiment, a differential amplifier is provided between the delay circuit and the current limiting circuit. This differential amplifier is typically needed in a case where VCC is not well-controlled to provide an output signal which has an appropriate voltage. A method of generating an oscillating output for refreshing a DRAM and a method for refreshing a DRAM are also disclosed.

摘要翻译： 使用恒流源来提供恒定电流来设定限定振荡器的输出周期的延迟。 延迟优选通过用恒定电流对电容器充电来设定。 由于电流与VCC和温度的变化无关，电容器将在给定的时间内充电。 因此，振荡的频率或周期也将是固定的，与VCC或温度的变化无关。 提供限流电路和锁存器以产生将通过一个或一系列逆变器传输的输出。 在替代实施例中，差分放大器设置在延迟电路和限流电路之间。 在VCC未被良好控制以提供具有适当电压的输出信号的情况下，通常需要该差分放大器。 还公开了一种产生用于刷新DRAM的振荡输出的方法和用于刷新DRAM的方法。

公开(公告)号：US5973980A

公开(公告)日：1999-10-26

申请号：US121253

申请日：1998-07-23

申请人： John William Tiede ,  Jon Allan Faue

发明人： John William Tiede ,  Jon Allan Faue

IPC分类号： G05F1/46 ,  G11C7/00

CPC分类号： G05F1/465

摘要： An on-chip voltage regulator for controlling a gate of a regulator transistor having a first terminal coupled to receive an external power supply voltage and a second terminal coupled to provide a regulated voltage level to an internal circuit formed on a chip on which the on-chip voltage regulator is formed. The on-chip voltage regulator includes circuitry for detecting when a high current load to which the second terminal of the regulator transistor is coupled is activated. A control transistor is provided having a first terminal coupled to receive the external power supply voltage, a second terminal coupled to the gate of the regulator transistor, and a gate responsive to the means for detecting. In operation, a control voltage with an overshoot portion having preselected duration is generated on the gate of the regulator transistor in response to the activation of the high current load.

摘要翻译： 一种用于控制具有耦合以接收外部电源电压的第一端子的稳压晶体管的栅极的片上电压调节器，以及耦合到对芯片上形成的内部电路提供调节的电压电平的第二端子， 形成片式稳压器。 片上电压调节器包括用于检测何时将稳压晶体管的第二端耦合到的高电流负载被激活的电路。 提供控制晶体管，其具有耦合以接收外部电源电压的第一端子，耦合到调节器晶体管的栅极的第二端子和响应于用于检测的装置的栅极。 在操作中，响应于高电流负载的激活，在调节晶体管的栅极上产生具有预选持续时间的过冲部分的控制电压。

公开(公告)号：US5869376A

公开(公告)日：1999-02-09

申请号：US709603

申请日：1996-09-09

申请人： Yugo Tomioka

发明人： Yugo Tomioka

IPC分类号： H01L21/76 ,  H01L21/765 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/08 ,  H01L27/108 ,  H01L21/00 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L21/765

摘要： The present invention has the object of offering a semiconductor production method which simplifies the fabrication of gate electrodes for MOS-type semiconductor elements and allows a high yield to be maintained. For this purpose, it has steps of forming a field-shield gate insulation film on a semiconductor substrate, forming polycrystalline silicon films having an etching rate which is greater at an upper side than a lower side thereon, and etching the polycrystalline silicon films under conditions which allow for side etching with the silicon oxide film as a mask, so as to make gradually tapered inclines on side walls of field-shield gate electrode.

摘要翻译： 本发明的目的是提供一种半导体制造方法，其简化了用于MOS型半导体元件的栅电极的制造，并且可以保持高产率。 为此，它具有在半导体衬底上形成场屏蔽栅绝缘膜的步骤，形成具有在其上侧比其下侧大的蚀刻速率的多晶硅膜，并且在条件下蚀刻多晶硅膜 这允许用氧化硅膜作为掩模进行侧面蚀刻，以便在场屏蔽栅电极的侧壁上逐渐变细的倾斜。