公开(公告)号：US20110186227A1

公开(公告)日：2011-08-04

申请号：US13084849

申请日：2011-04-12

Applicant: Gregory S. Sexton ,  Andrew D. Bailey, III ,  Andras Kuthi

Inventor： Gregory S. Sexton ,  Andrew D. Bailey, III ,  Andras Kuthi

IPC: B08B13/00 ,  C23F1/08

CPC classification number: H01L21/02087 ,  B08B7/0035 ,  H01J37/32091 ,  H01J37/32174 ,  H01J37/32541 ,  H01L21/67069

Abstract: The embodiments provide structures and mechanisms for removal of etch byproducts, dielectric films and metal films on and near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In one example, a chamber for wafer bevel edge cleaning is provided. The chamber includes a bottom electrode having a bottom electrode surface for supporting the wafer when present. Also included is a top edge electrode surrounding an insulating plate. The insulator plate is opposing the bottom electrode. The top edge electrode is electrically grounded and has a down-facing L shape. Further included in the chamber is a bottom edge electrode that is electrically grounded and spaced apart from the bottom electrode. The bottom edge electrode is disposed to encircle the bottom electrode. The bottom edge electrode is oriented to oppose the down-facing L shape of the top edge electrode.

Abstract translation: 这些实施例提供用于去除基板斜边缘上和附近的蚀刻副产物，电介质膜和金属膜的结构和机构，以及室内，以避免聚合物副产物和沉积膜的积聚并提高工艺产率。 在一个示例中，提供了用于晶片斜面边缘清洁的室。 该室包括底部电极，其具有用于在存在时支撑晶片的底部电极表面。 还包括围绕绝缘板的顶边电极。 绝缘板与底部电极相对。 顶边电极电接地并具有向下的L形状。 还包括在腔室中的底边电极是电接地的并且与底部电极间隔开。 下边缘电极被设置成环绕底部电极。 底部边缘电极被定向成与顶部边缘电极的向下的L形相对。

公开(公告)号：US07943007B2

公开(公告)日：2011-05-17

申请号：US11698190

申请日：2007-01-26

Applicant: Andrew D. Bailey, III ,  Alan M. Schoepp ,  Gregory Sexton ,  Yunsang Kim ,  William S. Kennedy

Inventor： Andrew D. Bailey, III ,  Alan M. Schoepp ,  Gregory Sexton ,  Yunsang Kim ,  William S. Kennedy

IPC: H01L21/00

CPC classification number: H01L21/0209 ,  H01J37/32366 ,  H01J37/32568 ,  H01J2237/335 ,  H01L21/67069

Abstract: A device for cleaning a bevel edge of a semiconductor substrate. The device includes: a lower support having a cylindrical top portion; a lower plasma-exclusion-zone (PEZ) ring surrounding the outer edge of the top portion and adapted to support the substrate; an upper dielectric component opposing the lower support and having a cylindrical bottom portion; an upper PEZ ring surrounding the outer edge of the bottom portion and opposing the lower PEZ ring; and at least one radiofrequency (RF) power source operative to energize process gas into plasma in an annular space defined by the upper and lower PEZ rings, wherein the annular space encloses the bevel edge.

Abstract translation: 一种用于清洁半导体衬底的斜边缘的装置。 该装置包括：具有圆柱形顶部的下支撑件; 围绕顶部部分的外边缘并适于支撑基底的较低等离子体排除区（PEZ）环; 与所述下支撑件相对并且具有圆柱形底部部分的上介电部件; 围绕底部的外边缘并与下部PEZ环相对的上部PEZ环; 以及至少一个射频（RF）电源，其用于在由所述上和下PEZ环限定的环形空间中将工艺气体激发成等离子体，其中所述环形空间包围所述斜面边缘。

公开(公告)号：US20100285671A1

公开(公告)日：2010-11-11

申请号：US12463155

申请日：2009-05-08

Applicant: Bing Ji ,  Andrew D. Bailey, III ,  Maryam Moravej ,  Stephen M. Sirard

Inventor： Bing Ji ,  Andrew D. Bailey, III ,  Maryam Moravej ,  Stephen M. Sirard

IPC: H01L21/3065

CPC classification number: H01L21/31138 ,  G03F7/427 ,  H01L21/31116

Abstract: A method for forming etched features in a low-k dielectric layer disposed below the photoresist mask in a plasma processing chamber is provided. Features are etched into the low-k dielectric layer through the photoresist mask. The photoresist mask is stripped, wherein the stripping comprising at least one cycle, wherein each cycle comprises a fluorocarbon stripping phase, comprising flowing a fluorocarbon stripping gas into the plasma processing chamber, forming a plasma from the fluorocarbon stripping gas, and stopping the flow of the fluorocarbon stripping gas into the plasma processing chamber and a reduced fluorocarbon stripping phase, comprising flowing a reduced fluorocarbon stripping gas that has a lower fluorocarbon flow rate than the fluorocarbon stripping gas into the plasma processing chamber, forming the plasma from the reduced fluorocarbon stripping gas, and stopping the flow of the reduced fluorocarbon stripping gas.

Abstract translation: 提供了一种用于在等离子体处理室中的光致抗蚀剂掩模下方形成低k电介质层中形成蚀刻特征的方法。 通过光致抗蚀剂掩模将特征蚀刻到低k电介质层中。 剥离光致抗蚀剂掩模，其中剥离包括至少一个循环，其中每个循环包括氟碳汽提相，包括将氟碳汽提气体流入等离子体处理室，从氟碳汽提气体形成等离子体，并停止 进入等离子体处理室中的碳氟化合物汽提气体和减少的氟碳汽提阶段，包括将具有低于碳氟化合物汽提气体的碳氟化合物流速低的氟化碳汽提气体流入等离子体处理室，从还原氟碳汽提气体形成等离子体 ，并停止还原氟烃剥离气体的流动。

公开(公告)号：US20100261352A1

公开(公告)日：2010-10-14

申请号：US12756086

申请日：2010-04-07

Applicant: Bing Ji ,  Kenji Takeshita ,  Andrew D. Bailey, III ,  Eric A. Hudson ,  Maryam Moravej ,  Stephen M. Sirard ,  Jungmin Ko ,  Daniel Le ,  Robert C. Hefty ,  Yu Cheng ,  Gerardo A. Delgadino ,  Bi-Ming Yen

Inventor： Bing Ji ,  Kenji Takeshita ,  Andrew D. Bailey, III ,  Eric A. Hudson ,  Maryam Moravej ,  Stephen M. Sirard ,  Jungmin Ko ,  Daniel Le ,  Robert C. Hefty ,  Yu Cheng ,  Gerardo A. Delgadino ,  Bi-Ming Yen

IPC: H01L21/467

CPC classification number: H01L21/31116 ,  H01L21/02063 ,  H01L21/31138

Abstract: A method for etching features in a low-k dielectric layer disposed below an organic mask is provided by an embodiment of the invention. Features are etched into the low-k dielectric layer through the organic mask. A fluorocarbon layer is deposited on the low-k dielectric layer. The fluorocarbon layer is cured. The organic mask is stripped.

Abstract translation: 通过本发明的实施例提供了一种用于蚀刻位于有机掩模下方的低k电介质层中的特征的方法。 通过有机掩模将特征蚀刻到低k电介质层中。 在低k电介质层上沉积氟碳层。 氟碳层被固化。 剥去有机面膜。

公开(公告)号：US20100100221A1

公开(公告)日：2010-04-22

申请号：US12653598

申请日：2009-12-15

Applicant: Puneet Yadav ,  Andrew D. Bailey, III

Inventor： Puneet Yadav ,  Andrew D. Bailey, III

IPC: G05B13/04 ,  G06F17/18 ,  G06F15/18

CPC classification number: G05B19/41875 ,  G05B2219/31352 ,  G05B2219/32191 ,  Y02P90/22

Abstract: A method for adjusting a data set defining a set of process runs, each process run having a set of data corresponding to a set of variables for a wafer processing operation is provided. A model derived from a data set is received. A new data set corresponding to one process run is received. The new data set is projected to the model. An outlier data point produced as a result of the projecting is identified. A variable corresponding to the one outlier data point is identified, the identified variable exhibiting a high contribution. A value for the variable from the new data set is identified. Whether the value for the variable is unimportant is determined. A normalized matrix of data is created, using random data and the variable that was determined to be unimportant from each of the new data set and the data set. The data set is updated with the normalized matrix of data.

公开(公告)号：US20100099265A1

公开(公告)日：2010-04-22

申请号：US12648264

申请日：2009-12-28

Applicant: HYUNGSUK ALEXANDER YOON ,  YUNSANG KIM ,  JASON A. RYDER ,  ANDREW D. BAILEY, III

Inventor： HYUNGSUK ALEXANDER YOON ,  YUNSANG KIM ,  JASON A. RYDER ,  ANDREW D. BAILEY, III

IPC: H01L21/3065

CPC classification number: H01L21/02087 ,  H01J37/32541 ,  H01J37/3255 ,  H05H1/2406 ,  H05H2001/2412

Abstract: A method for generating plasma for removing an edge polymer from a substrate is provided. The method includes providing a powered electrode assembly, which includes a powered electrode, a dielectric layer, and a wire mesh disposed between the powered electrode and the dielectric layer. The method also includes providing a grounded electrode assembly disposed opposite the powered electrode assembly to form a cavity wherein the plasma is generated. The wire mesh is shielded from the plasma by the dielectric layer when the plasma is present in the cavity, which has an outlet at one end for providing the plasma to remove the edge polymer. The method further includes introducing at least one inert gas and at least one process gas into the cavity. The method yet also includes applying an RF field to the cavity using the powered electrode to generate the plasma from the inert gas and process gas.

Abstract translation: 提供了一种用于从衬底除去边缘聚合物的等离子体的方法。 该方法包括提供一种动力电极组件，其包括供电电极，电介质层和布置在电源电极和电介质层之间的金属丝网。 该方法还包括提供与动力电极组件相对设置的接地电极组件，以形成其中产生等离子体的空腔。 当等离子体存在于空腔中时，金属丝网通过电介质层被屏蔽，等离子体在一端具有出口，用于提供等离子体以去除边缘聚合物。 该方法还包括将至少一种惰性气体和至少一种工艺气体引入空腔中。 该方法还包括使用动力电极将RF场施加到空腔，以从惰性气体和处理气体产生等离子体。

公开(公告)号：US07611640B1

公开(公告)日：2009-11-03

申请号：US11396124

申请日：2006-03-30

Applicant: Arthur M Howald ,  Andras Kuthi ,  Andrew D. Bailey, III ,  Butch Berney

Inventor： Arthur M Howald ,  Andras Kuthi ,  Andrew D. Bailey, III ,  Butch Berney

IPC: C23F1/00 ,  H01L21/3065

CPC classification number: H01J37/32477 ,  H01J37/32623

Abstract: A plasma processing chamber for processing a substrate to form electronic components thereon is disclosed. The plasma processing chamber includes a plasma-facing component having a plasma-facing surface oriented toward a plasma in the plasma processing chamber during processing of the substrate, the plasma-facing component being electrically isolated from a ground terminal. The plasma processing chamber further includes a grounding arrangement coupled to the plasma-facing component, the grounding arrangement including a first resistance circuit disposed in a first current path between the plasma-facing component and the ground terminal. The grounding arrangement further includes a RF filter arrangement disposed in at least one other current path between the plasma-facing component and the ground terminal, wherein a resistance value of the first resistance circuit is selected to substantially eliminate arcing between the plasma and the plasma-facing component during the processing of the substrate.

Abstract translation: 公开了一种用于处理基板以在其上形成电子部件的等离子体处理室。 等离子体处理室包括在基板处理期间具有朝向等离子体处理室中的等离子体的表面等离子体表面的等离子体面向部件，等离子体面向部件与接地端子电隔离。 等离子体处理室还包括耦合到等离子体面向部件的接地装置，接地装置包括设置在等离子体面向部件和接地端子之间的第一电流路径中的第一电阻电路。 接地装置还包括设置在等离子体面向部件和接地端子之间的至少一个其它电流通路中的RF滤波器装置，其中选择第一电阻电路的电阻值以基本上消除等离子体和等离子体 - 在处理基板期间面对部件。

公开(公告)号：US07575638B2

公开(公告)日：2009-08-18

申请号：US11701854

申请日：2007-02-02

Applicant: Andrew D. Bailey, III ,  Jack Chen ,  Yunsang Kim ,  Gregory S. Sexton

Inventor： Andrew D. Bailey, III ,  Jack Chen ,  Yunsang Kim ,  Gregory S. Sexton

IPC: B05B5/025 ,  C23C16/00 ,  C23F1/00 ,  H01L21/306

CPC classification number: H01L21/67069 ,  H01J37/32568 ,  H01L21/68721

Abstract: Positional relationships are established in a process chamber. An upper electrode is configured with a first surface to support a wafer, and an electrode has a second surface. A linear drive is mounted on the base and a linkage connected between the drive and the upper electrode. Linkage adjustment defines a desired orientation between the surfaces. The linear drive and linkage maintain the desired orientation while the assembly moves the upper electrode with the surfaces moving relative to each other. An annular etching region defined between the electrodes enables etching of a wafer edge exclusion region extending along a top and bottom of the wafer. Removable etch defining rings are configured to define unique lengths along each of the top and bottom of the wafer to be etched. Positional relationships of the surfaces enable limiting the etching to those unique lengths of the exclusion region.

Abstract translation: 位置关系建立在一个过程室中。 上电极配置有第一表面以支撑晶片，并且电极具有第二表面。 线性驱动器安装在基座上，连接在驱动器和上电极之间。 连接调整定义了表面之间的期望取向。 线性驱动器和连接件保持所需的取向，同时组件移动上电极，表面相对于彼此移动。 限定在电极之间的环形蚀刻区域能够蚀刻沿着晶片的顶部和底部延伸的晶片边缘排除区域。 可移除蚀刻限定环被配置为沿待蚀刻的晶片的顶部和底部的每一个限定独特的长度。 表面的位置关系使得能够将蚀刻限制到排除区域的那些独特长度。

公开(公告)号：US20090166326A1

公开(公告)日：2009-07-02

申请号：US11758584

申请日：2007-06-05

Applicant: Gregory S. Sexton ,  Andrew D. Bailey, III ,  Andras Kuthi ,  Yunsang Kim

Inventor： Gregory S. Sexton ,  Andrew D. Bailey, III ,  Andras Kuthi ,  Yunsang Kim

IPC: C23F1/00

CPC classification number: H01L21/02087 ,  H01J37/32009 ,  H01J37/32082 ,  H01J37/32559 ,  H01J37/32642 ,  H01J37/32862 ,  H01L21/02057 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136

Abstract: The embodiments provide apparatus and methods for removal of etch byproducts, dielectric films and metal films near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In an exemplary embodiment, a plasma processing chamber configured to clean a bevel edge of a substrate is provided. The plasma processing chamber includes a substrate support configured to receive the substrate. The plasma processing chamber also includes a bottom edge electrode surrounding the substrate support. The bottom edge electrode and the substrate support are electrically isolated from one another by a bottom dielectric ring. A surface of the bottom edge electrode facing the substrate is covered by a bottom thin dielectric layer. The plasma processing chamber further includes a top edge electrode surrounding a top insulator plate opposing the substrate support. The top edge electrode is electrically grounded. A surface of the top edge electrode facing the substrate is covered by a top thin dielectric layer. The top edge electrode and the bottom edge electrode oppose one another and are configured to generate a cleaning plasma to clean the bevel edge of the substrate.

Abstract translation: 这些实施例提供用于去除蚀刻副产物，电介质膜和金属膜附近的衬底斜面边缘的设备和方法，以及室内，以避免聚合物副产物和沉积膜的堆积并提高工艺产率。 在示例性实施例中，提供了构造成清洁基板的斜边缘的等离子体处理室。 等离子体处理室包括被配置为接收衬底的衬底支撑件。 等离子体处理室还包括围绕衬底支撑件的底部边缘电极。 底部边缘电极和基底支撑件通过底部介电环彼此电隔离。 面向基板的底部边缘电极的表面被底部薄的电介质层覆盖。 等离子体处理室还包括围绕与衬底支撑件相对的顶部绝缘体板的顶部边缘电极。 顶边电极电接地。 面向衬底的顶边电极的表面被顶部薄介电层覆盖。 顶边电极和下边缘电极彼此相对并且被配置为产生清洁等离子体以清洁衬底的斜边缘。

公开(公告)号：US20080182412A1

公开(公告)日：2008-07-31

申请号：US11698190

申请日：2007-01-26

Applicant: Andrew D. Bailey III ,  Alan M. Schoepp ,  Gregory Sexton ,  Yunsang Kim ,  William S. Kennedy

Inventor： Andrew D. Bailey III ,  Alan M. Schoepp ,  Gregory Sexton ,  Yunsang Kim ,  William S. Kennedy

IPC: C23F1/00 ,  H01L21/306 ,  H01L21/302

CPC classification number: H01L21/0209 ,  H01J37/32366 ,  H01J37/32568 ,  H01J2237/335 ,  H01L21/67069

Abstract: A device for cleaning a bevel edge of a semiconductor substrate. The device includes: a lower support having a cylindrical top portion; a lower plasma-exclusion-zone (PEZ) ring surrounding the outer edge of the top portion and adapted to support the substrate; an upper dielectric component opposing the lower support and having a cylindrical bottom portion; an upper PEZ ring surrounding the outer edge of the bottom portion and opposing the lower PEZ ring; and at least one radiofrequency (RF) power source operative to energize process gas into plasma in an annular space defined by the upper and lower PEZ rings, wherein the annular space encloses the bevel edge.

Abstract translation: 一种用于清洁半导体衬底的斜边缘的装置。 该装置包括：具有圆柱形顶部的下支撑件; 围绕顶部部分的外边缘并适于支撑基底的较低等离子体排除区（PEZ）环; 与所述下支撑件相对并且具有圆柱形底部部分的上介电部件; 围绕底部的外边缘并与下部PEZ环相对的上部PEZ环; 以及至少一个射频（RF）电源，其用于在由所述上和下PEZ环限定的环形空间中将工艺气体激发成等离子体，其中所述环形空间包围所述斜面边缘。