公开(公告)号：US20110031562A1

公开(公告)日：2011-02-10

申请号：US12757241

申请日：2010-04-09

Applicant: Yu Chao LIN ,  Jr Jung LIN ,  Yih-Ann LIN ,  Jih-Jse LIN ,  Chao-Cheng CHEN ,  Ryan Chia-Jen CHEN ,  Weng CHANG

Inventor： Yu Chao LIN ,  Jr Jung LIN ,  Yih-Ann LIN ,  Jih-Jse LIN ,  Chao-Cheng CHEN ,  Ryan Chia-Jen CHEN ,  Weng CHANG

IPC: H01L29/78

CPC classification number: H01L29/4983 ,  H01L29/6656

Abstract: An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.

Abstract translation: 场效应晶体管的栅极结构的示例性结构包括栅电极; 栅电极下方的栅极绝缘体，在栅电极的相对侧具有基极区域; 以及在所述栅极结构的侧壁上的密封层，其中覆盖所述基底区域的所述密封层的下部的厚度小于所述栅电极的侧壁上的所述密封层的上部的厚度，由此所述场效应晶体管 在基板表面几乎没有凹陷。

公开(公告)号：US07759239B1

公开(公告)日：2010-07-20

申请号：US12435552

申请日：2009-05-05

Applicant: Yu Chao Lin ,  De-Fang Chen ,  Chia-Wei Chang ,  Yih-Ann Lin ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Weng Cheng

Inventor： Yu Chao Lin ,  De-Fang Chen ,  Chia-Wei Chang ,  Yih-Ann Lin ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Weng Cheng

IPC: H01L21/3205

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/31144

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate layer over a substrate, forming a hard mask layer over a gate layer, forming a first material layer over the hard mask layer, forming a patterned photoresist layer having an opening over the first material layer, etching the first material layer through a cycle including forming a second material layer over the semiconductor device and etching the first and second material layers, repeating the cycle until the hard mask layer is exposed by a reduced opening, the reduced opening formed in a last cycle, etching the hard mask layer beneath the second opening to expose the gate layer, and patterning the gate layer using the hard mask layer. An etching selectivity of the first and second material layers is smaller than an etching selectivity of the second material layer and the photoresist layer.

Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成栅极层，在栅极层上形成硬掩模层，在硬掩模层上形成第一材料层，形成在第一材料层上具有开口的图案化光刻胶层，蚀刻第一材料 层，其包括在半导体器件上形成第二材料层并蚀刻第一和第二材料层，重复该循环，直到硬掩模层通过减小的开口暴露，在最后一个循环中形成的减小的开口，蚀刻硬 掩模层以暴露栅极层，并且使用硬掩模层图案化栅极层。 第一和第二材料层的蚀刻选择性小于第二材料层和光致抗蚀剂层的蚀刻选择性。

公开(公告)号：US20100068861A1

公开(公告)日：2010-03-18

申请号：US12339483

申请日：2008-12-19

Applicant: Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Joseph Lin ,  Jr Jung Lin ,  Yu Chao Lin ,  Chao-Cheng Chen ,  Kuo-Tai Huang

Inventor： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Joseph Lin ,  Jr Jung Lin ,  Yu Chao Lin ,  Chao-Cheng Chen ,  Kuo-Tai Huang

IPC: H01L21/8234 ,  H01L21/28

CPC classification number: H01L29/7848 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636

Abstract: Provided is a method of semiconductor fabrication including process steps allowing for defining and/or modifying a gate structure height during the fabrication process. The gate structure height may be modified (e.g., decreased) at one or more stages during the fabrication by etching a portion of a polysilicon layer included in the gate structure. The method includes forming a coating layer on the substrate and overlying the gate structure. The coating layer is etched back to expose a portion of the gate structure. The gate structure (e.g., polysilicon) is etched back to decrease the height of the gate structure.

Abstract translation: 提供了一种半导体制造方法，包括允许在制造过程期间限定和/或修改栅极结构高度的工艺步骤。 栅极结构高度可以在制造期间的一个或多个阶段被修改（例如减小），通过蚀刻包括在栅极结构中的多晶硅层的一部分。 该方法包括在衬底上形成覆盖层并覆盖栅极结构。 将涂层回蚀刻以露出栅极结构的一部分。 蚀刻栅极结构（例如，多晶硅）以降低栅极结构的高度。

公开(公告)号：US07511349B2

公开(公告)日：2009-03-31

申请号：US11207450

申请日：2005-08-19

Applicant: Ming-Huan Tsai ,  Fang-Cheng Chen ,  Chao-Cheng Chen ,  Syun-Ming Jang

Inventor： Ming-Huan Tsai ,  Fang-Cheng Chen ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/00 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76897 ,  H01L21/76804 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit chip includes a buffer layer, an underlying layer, a dielectric layer, a hole, and barrier layer. The buffer layer is over the underlying layer. The dielectric layer is over the buffer layer. The hole is formed in and extending through the dielectric layer and the buffer layer, and opens to the underlying layer. The hole includes a buffer layer portion at the buffer layer and a dielectric layer portion at the dielectric layer. At least part of the buffer layer portion of the hole has a larger cross-section area than a smallest cross-section area of the dielectric layer portion of the hole. The conformal barrier layer covers surfaces of the dielectric layer and the buffer layer in the hole. The hole is a via hole or a contact hole that is later filled with a conductive material to form a conductive via or a conductive contact.

Abstract translation: 集成电路芯片包括缓冲层，下层，电介质层，空穴和阻挡层。 缓冲层位于底层之上。 电介质层在缓冲层之上。 孔形成并延伸穿过介电层和缓冲层，并向下层开放。 该孔包括在缓冲层处的缓冲层部分和介电层处的电介质层部分。 孔的缓冲层部分的至少一部分具有比孔的电介质层部分的最小横截面面积更大的横截面面积。 保形阻挡层覆盖孔中的介电层和缓冲层的表面。 孔是通孔或接触孔，其后面填充有导电材料以形成导电通孔或导电接触。

公开(公告)号：US07186662B2

公开(公告)日：2007-03-06

申请号：US10964841

申请日：2004-10-13

Applicant: Chien-Hao Chen ,  Chia-Jen Chen ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Shih-Chang Chen

Inventor： Chien-Hao Chen ,  Chia-Jen Chen ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Shih-Chang Chen

IPC: H01L21/461

CPC classification number: H01L21/28123 ,  H01L21/0217 ,  H01L21/28035 ,  H01L21/31608 ,  H01L21/3185

Abstract: A method for forming a hard mask for gate electrode patterning in a semiconductor device is disclosed. The method includes providing a polysilicon layer to be etched and forming over the polysilicon layer, a nitride hardmask with a relatively high etch rate to hydrofluoric acid, as compared to the etch rate of silicon oxide. The polysilicon can then be patterned using the hardmask and the hardmask can be removed using hydrofluoric acid.

Abstract translation: 公开了一种在半导体器件中形成用于栅电极图案化的硬掩模的方法。 该方法包括提供待蚀刻并在多晶硅层上形成的多晶硅层，与氧化硅的蚀刻速率相比，具有对氢氟酸的蚀刻速率相对较高的氮化物硬掩模。 然后可以使用硬掩模对多晶硅进行图案化，并且可以使用氢氟酸去除硬掩模。

公开(公告)号：US07033518B2

公开(公告)日：2006-04-25

申请号：US10602968

申请日：2003-06-24

Applicant: Hui Ou Yang ,  Miao-Ju Hsu ,  Chao-Cheng Chen ,  Hun-Jan Tao

Inventor： Hui Ou Yang ,  Miao-Ju Hsu ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC: H01L21/00

CPC classification number: H01L21/31116 ,  H01J37/32935 ,  H01L22/26

Abstract: A method of etching multi-layer films, the method including: (1) etching a plurality of layers according to etching parameters, (2) determining a plurality of optical characteristics each associated with one of the plurality of layers and determined during the etching of the associated one of the plurality of layers, and (3) determining dynamic etch progressions each based on one of the plurality of optical characteristics that is associated with a particular one of the plurality of layers undergoing the etching.

Abstract translation: 一种蚀刻多层膜的方法，所述方法包括：（1）根据蚀刻参数蚀刻多个层，（2）确定多个光学特性，每个光学特性与所述多个层之一相关联并且在蚀刻期间确定 所述多个层中的相关联的一个层，以及（3）基于所述多个光学特性之一确定动态蚀刻进展，所述多个光学特性与经历所述蚀刻的所述多个层中的特定一个层相关联。

公开(公告)号：US20050136678A1

公开(公告)日：2005-06-23

申请号：US10743979

申请日：2003-12-22

Applicant: Chun-Li Chou ,  Yih-Ann Lin ,  Yi-Chen Huang ,  Chao-Cheng Chen ,  Hun-Jan Tao

Inventor： Chun-Li Chou ,  Yih-Ann Lin ,  Yi-Chen Huang ,  Chao-Cheng Chen ,  Hun-Jan Tao

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/02071 ,  H01L21/02063 ,  H01L21/76807

Abstract: A method for cleaning semiconductor substrates includes a DI water clean operation that uses a spin speed no greater than 350 rpm. The cleaning method may include additional cleaning operations such as an organic clean, an aqueous chemical clean or a DI water/ozone clean. The cleaning method may be used to clean substrates after the conclusion of an etching procedure which exposes a single film between a Cu-containing conductive material and the environment. The spin speed of the DI water clean operation prevents copper corrosion due to breakdown of the film that separates the Cu-containing conductive material from the environment.

Abstract translation: 用于清洁半导体衬底的方法包括使用不大于350rpm的旋转速度的去离子水清洁操作。 清洁方法可以包括附加的清洁操作，例如有机清洁剂，水性化学清洁剂或去离子水/臭氧清洁剂。 在完成了在含Cu导电材料和环境之间暴露单个膜的蚀刻过程结束之前，清洁方法可用于清洁衬底。 去离子水清洁操作的旋转速度可防止由于将含Cu导电材料与环境分离的膜破裂导致铜腐蚀。

公开(公告)号：US06790770B2

公开(公告)日：2004-09-14

申请号：US10035690

申请日：2001-11-08

Applicant: Chao-Cheng Chen ,  Jen-Cheng Liu ,  Jyu-Horng Shieh

Inventor： Chao-Cheng Chen ,  Jen-Cheng Liu ,  Jyu-Horng Shieh

IPC: H01L214763

CPC classification number: H01L21/76808

Abstract: A method if provided for improving a photolithographic patterning process in a dual damascene process by forming a resinous plug in a via opening to prevent out diffusion of nitrogen containing species from a low-k IMD layer in subsequent lithographic patterning and RIE etching processes to form a trench opening formed substantially over the via opening.

Abstract translation: 如果提供用于通过在通孔开口中形成树脂塞以改善来自低k IMD层的含氮物质的扩散的方法，以在随后的平版印刷图案化和RIE蚀刻工艺中形成二维镶嵌工艺中的光刻图案化方法 沟槽开口基本上形成在通孔开口上方。

公开(公告)号：US06323121B1

公开(公告)日：2001-11-27

申请号：US09570018

申请日：2000-05-12

Applicant: Jen-Cheng Liu ,  Chao-Cheng Chen ,  Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui

Inventor： Jen-Cheng Liu ,  Chao-Cheng Chen ,  Li-Chih Chao ,  Chia-Shiung Tsai ,  Ming-Huei Lui

IPC: H01L214763

CPC classification number: H01L21/02063 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76807

Abstract: A method is described for cleaning freshly etched dual damascene via openings and preparing them for copper fill without damage or contamination of exposed organic or other porous low-k insulative layers. The method is entirely dry and does not expose the porous materials to contamination from moisture or solvents. The method is effective for removing all traces of residual polymer deposits from an in-process substrate wafers after via or damascene trench etching. The method employs an in-situ three-step treatment comprising a first step of exposing the electrically biased substrate wafer to a O2/N2 ashing plasma to remove photoresist and polymers, a second step immediately following the first step of remove silicon nitride etch stop layers, and a final step of treating the wafer with H2/N2 to remove copper polymer deposits formed during nitride removal. The H2/N2 plasma is capable of removing the difficult polymer residues which are otherwise only removable by wet stripping procedures. The H2/N2 plasma is not harmful to exposed porous low-k dielectric layers as well as copper metallurgy.

Abstract translation: 描述了一种用于通过开口清洁新鲜蚀刻的双镶嵌件的方法，并且它们用于铜填充而不损坏或污染暴露的有机或其它多孔低k绝缘层。 该方法是完全干燥的，并且不会使多孔材料暴露于水分或溶剂的污染物中。 该方法对于在通孔或镶嵌沟槽蚀刻之后从工艺衬底晶片去除残余聚合物沉积物的所有迹线是有效的。 该方法采用原位三步处理，其包括将电偏置的衬底晶片暴露于O 2 / N 2灰分等离子体以去除光致抗蚀剂和聚合物的第一步骤，紧接着在去除氮化硅蚀刻停止层的第一步骤之后的第二步骤 ，以及用H2 / N2处理晶片以除去在氮化物除去期间形成的铜聚合物沉积物的最后步骤。 H 2 / N 2等离子体能够去除困难的聚合物残余物，否则其仅可通过湿式剥离方法除去。 H2 / N2等离子体对暴露的多孔低k电介质层以及铜冶金无害。

公开(公告)号：US6133145A

公开(公告)日：2000-10-17

申请号：US169434

申请日：1998-10-09

Applicant: Chao-Cheng Chen

Inventor： Chao-Cheng Chen

IPC: H01L21/027 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/32139 ,  H01L21/0273 ,  H01L21/76838

Abstract: A process for fabricating an aluminum based interconnect structure, using a plasma treated photoresist shape as an etch mask, has been developed. The process features treating a photoresist shape, to be used as an etch mask during RIE patterning procedures, in a nitrogen containing plasma. The plasma nitrogen treated photoresist shape is eroded at a decreased rate, when compared to counterpart non-treated photoresist shapes, during the RIE procedure used to fabricate the aluminum based interconnect structure. The increased etch rate ratio, between layers used for the interconnect structure, and the plasma treated photoresist shape, allows thinner photoresist shapes to be used, and therefore allows narrower lines and spaces to be achieved.

Abstract translation: 已经开发了使用等离子体处理的光致抗蚀剂形状作为蚀刻掩模来制造铝基互连结构的方法。 该方法的特征是在含氮等离子体中处理光刻胶形状，以在RIE图案化步骤期间用作蚀刻掩模。 在用于制造铝基互连结构的RIE程序期间，与对照未处理的光致抗蚀剂形状相比，等离子体氮处理的光致抗蚀剂形状以降低的速率被侵蚀。 用于互连结构的层之间的增加的蚀刻速率比和等离子体处理的光致抗蚀剂形状允许使用更薄的光致抗蚀剂形状，因此允许实现更窄的线和空间。