公开(公告)号：US20070052079A1

公开(公告)日：2007-03-08

申请号：US11219815

申请日：2005-09-07

申请人： Chen-Jung Tsai ,  Chih-Wen Lin

发明人： Chen-Jung Tsai ,  Chih-Wen Lin

IPC分类号： H01L23/02

CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/49175 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A multi-chip stacked package structure, including a leadframe base thin package structure with two or more chips in the stacking structure, is provided that is capable of including two or more stacked chips that reduce the total stacking thickness. The package structure also reduces stacking thickness by achieving stacking of four or more chips into the area of a thin small outline package structure.

摘要翻译： 提供了一种多芯片堆叠封装结构，其包括具有堆叠结构中的两个或更多个芯片的引线框底部薄封装结构，其能够包括减少总层叠厚度的两个或更多个堆叠芯片。 封装结构还通过实现将四个或更多个芯片堆叠到薄的小外形封装结构的区域中来减少堆叠厚度。

公开(公告)号：US07122904B2

公开(公告)日：2006-10-17

申请号：US10131485

申请日：2002-04-25

申请人： Chen-Jung Tsai ,  Jui-Chung Lee ,  Chih-Wen Lin

发明人： Chen-Jung Tsai ,  Jui-Chung Lee ,  Chih-Wen Lin

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5389 ,  H01L23/49816 ,  H01L24/19 ,  H01L25/0652 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/18162 ,  H01L2924/00

摘要： A semiconductor packaging device comprises a carrier having at least a cavity or a slot thereon. At least a chip has a back surface and an active surface with a plurality of first bonding pads. The chip is affixed to the cavity to expose the active surface. A first insulating layer is on the active surface and the carrier, which comprises first via-conductor connected to first bonding pads and via the first insulating layer. A multi-layer structure on the first insulating layer comprises a plurality of conductive layout lines, second via-conductor therein, and a second insulating layer, exposed ball pads, and flip-chip pads thereon. The first via-conductor are electrically connected with the conductive layout lines, the second via-conductor, the exposed ball pads, and the flip-chip pads. The first solder balls are affixed to the ball pads, and at least a second chip is affixed to the flip-chip pads through a plurality of second solder balls.

公开(公告)号：US06977436B2

公开(公告)日：2005-12-20

申请号：US10074052

申请日：2002-02-14

申请人： Chen-Jung Tsai ,  Jui-Chung Lee ,  Chih-Wen Lin

发明人： Chen-Jung Tsai ,  Jui-Chung Lee ,  Chih-Wen Lin

IPC分类号： H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/48

CPC分类号： H01L23/5389 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49822 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532

摘要： A semiconductor packaging device has a carrier having at least a portion configured for containing a chip. The chip, affixing to the portion with sidewall, has a back surface an active surface, which multitudes of bonding pads are on the active surface. One insulating layer on the active surface and carrier has multitudes of conductive holes corresponding to the first bonding pads. A multi-layer structure on the insulating layer is configured for providing electrical connection to the conductive holes. Another insulating layer, affixed on one of the carrier and the multi-layer structure, has another conductive holes electrically connected to the conductive holes. Multitudes of solder balls, on at least one of the carrier and latter insulating layer, electrically connect the latter conductive holes.

摘要翻译： 半导体封装装置具有至少一部分被配置为容纳芯片的载体。 固定在具有侧壁的部分上的芯片具有背表面，其中多个接合焊盘位于活性表面上。 有源表面和载体上的一个绝缘层具有对应于第一接合焊盘的多个导电孔。 绝缘层上的多层结构构造成用于提供与导电孔的电连接。 固定在载体和多层结构之一上的另一绝缘层具有电连接到导电孔的另一导电孔。 在载体和后一绝缘层中的至少一个上的大量焊球电连接后面的导电孔。

公开(公告)号：US20050001328A1

公开(公告)日：2005-01-06

申请号：US10726577

申请日：2003-12-04

申请人： Chen-Jung Tsai ,  Chih-Wen Lin

发明人： Chen-Jung Tsai ,  Chih-Wen Lin

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A dual chips stacked packaging structure. A first chip comprises an active surface and an opposing non-active surface, the active surface consisting of a central area and a peripheral area having a plurality of first bonding pads. A lead frame comprises a plurality of leads and a chip paddle having a first adhering surface and a second adhering surface, with the first adhering surface adhering to the active surface of the first chip in such a way as to avoid contact with the first bonding pads. A second chip comprises an active surface and an opposing non-active surface connecting with the second adhering surface of the chip paddle, and the active surface consisting of a central area and a peripheral area having a plurality of second bonding pads. Parts of the wires electrically connect with the first bonding pad and the leads, and parts of the wires electrically connect with the second bonding pad and the leads.

摘要翻译： 双芯片堆叠包装结构。 第一芯片包括有源表面和相对的非活性表面，活性表面由具有多个第一键合焊盘的中心区域和外围区域组成。 引线框架包括多个引线和具有第一粘附表面和第二粘附表面的芯片焊盘，其中第一粘附表面粘附到第一芯片的有效表面以避免与第一焊盘接触 。 第二芯片包括与芯片焊盘的第二粘附表面连接的有源表面和相对的非有效表面，以及由具有多个第二焊盘的中心区域和外围区域组成的活性表面。 导线的一部分与第一焊盘和引线电连接，并且导线的一部分与第二焊盘和引线电连接。

公开(公告)号：US06559526B2

公开(公告)日：2003-05-06

申请号：US09842133

申请日：2001-04-26

申请人： Jui-Chung Lee ,  Chen-Jung Tsai ,  Chih-Wen Lin

发明人： Jui-Chung Lee ,  Chen-Jung Tsai ,  Chih-Wen Lin

IPC分类号： H01L23495

CPC分类号： H01L23/49575 ,  H01L23/49513 ,  H01L23/49551 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2224/45015 ,  H01L2924/207

摘要： A structure of a stacked-type multi-chip stack package of the leadframe, the shape of the stair-like inner leads can be regulated for the high and the amount of stacked chips and to match different bonding technology. The process for forming the present structure can be easily performed by visible equipment and materials, and the present structure can raise the reliability of bonding process. The present invention can stack multi-chip (more than two).

摘要翻译： 可以调节引线框的堆叠式多芯片堆叠封装的结构，对于堆叠芯片的高和量来调节阶梯式内部引线的形状，并且可以匹配不同的焊接技术。 用于形成本结构的方法可以通过可见的设备和材料容易地进行，并且本结构可以提高接合过程的可靠性。 本发明可以堆叠多芯片（多于两个）。

公开(公告)号：US20120206784A1

公开(公告)日：2012-08-16

申请号：US13029112

申请日：2011-02-16

申请人： Yick Chuen CHAN ,  Siu Wai Lam ,  Lo Ming FOK ,  Ying LIU ,  Chen Jung TSAI

发明人： Yick Chuen CHAN ,  Siu Wai Lam ,  Lo Ming FOK ,  Ying LIU ,  Chen Jung TSAI

IPC分类号： G02B26/10 ,  G02B27/48 ,  G02B26/08

CPC分类号： G02B27/48 ,  G02B26/0833 ,  G02B26/101

摘要： The present invention relates to a method and apparatus for speckle noise reduction in laser scanning projection display. In particular, a MEMS device with a vibrating membrane through which light rays are refracted with temporally varying angles is provided for reducing the effect of speckling.

摘要翻译： 本发明涉及一种激光扫描投影显示中散斑噪声降低的方法和装置。 特别地，提供具有振动膜的MEMS装置，通过该振动膜，光线随时间变化的角度折射，以减少斑点的影响。

公开(公告)号：US08243007B2

公开(公告)日：2012-08-14

申请号：US12125360

申请日：2008-05-22

申请人： Wei Zhang ,  Huajun Peng ,  Chen-Jung Tsai ,  Chun-Kit Hung

发明人： Wei Zhang ,  Huajun Peng ,  Chen-Jung Tsai ,  Chun-Kit Hung

IPC分类号： G09G3/36

CPC分类号： G09G3/3611 ,  G09G2320/062 ,  G09G2360/144 ,  G09G2360/16

摘要： An image display device is presented to solve problems of high power consumption, insufficient contrast, image flicker, and distortion of image display devices. The image display device includes an image display management module which includes a backlight control unit. The backlight control unit includes an image brightness analyzer, generating a brightness value according to an input image data; a weight generator, generating a weight according to the brightness value; an image variation analyzer, analyzing the input image data to generate an image variance; and a backlight factor generator, coupled to the weight generator and the image variation analyzer to generate a backlight adjusting signal according to the weight and the image variance. By the backlight adjusting signal, the image display device achieves the power-saving and contrast enhancement effects.

摘要翻译： 提出了一种图像显示装置，用于解决图像显示装置的高功耗，对比度不足，图像闪烁和失真的问题。 图像显示装置包括：图像显示管理模块，其包括背光控制单元。 背光控制单元包括图像亮度分析器，根据输入图像数据生成亮度值; 权重发生器，根据亮度值产生重量; 图像变化分析器，分析输入图像数据以产生图像方差; 以及背光源发生器，耦合到重量发生器和图像变化分析器，以根据重量和图像方差产生背光调节信号。 通过背光调整信号，图像显示装置实现了省电和对比度增强效果。

公开(公告)号：US08207931B2

公开(公告)日：2012-06-26

申请号：US11809095

申请日：2007-05-31

申请人： Wei Zhang ,  Huajun Peng ,  Chen-Jung Tsai

发明人： Wei Zhang ,  Huajun Peng ,  Chen-Jung Tsai

IPC分类号： G09G3/36 ,  G09G5/02

CPC分类号： G09G3/3426 ,  G09G3/3611 ,  G09G2320/064 ,  G09G2320/0646 ,  G09G2320/066 ,  G09G2340/0428

摘要： A method of increasing the dynamic range of an image comprising a plurality of pixels each having a luminance value within a first luminance dynamic range. The method includes determining a background luminance value for each pixel of the image and determining a minimum and a maximum of the background luminance values. A conversion factor is then determined for each pixel of the image based on the minimum and maximum of the background luminance values. The image id converted from the first luminance dynamic range to a second luminance dynamic range by multiplying the luminance value of each pixel of the image by its conversion factor.

摘要翻译： 一种增加包括多个像素的图像的动态范围的方法，每个像素具有在第一亮度动态范围内的亮度值。 该方法包括确定图像的每个像素的背景亮度值并确定背景亮度值的最小值和最大值。 然后基于背景亮度值的最小值和最大值确定图像的每个像素的转换因子。 通过将图像的每个像素的亮度值乘以其转换因子，从第一亮度动态范围转换成第二亮度动态范围的图像ID。

公开(公告)号：US07755188B2

公开(公告)日：2010-07-13

申请号：US12250979

申请日：2008-10-14

申请人： Chen Jung Tsai ,  Chin Wen Lin

发明人： Chen Jung Tsai ,  Chin Wen Lin

IPC分类号： H01L23/34

CPC分类号： H01L23/49575 ,  H01L23/481 ,  H01L2224/16 ,  H01L2924/01057

摘要： An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on the leadframe are facilitated by bonding pads on chip active surfaces and by via that extend from the bonding pads through the chips to the back surfaces.

摘要翻译： 描述了一种有效的芯片堆叠结构，其包括具有两个表面的引线框架，其中每一个可以附接芯片堆叠。 可以通过将芯片有源表面放置在另一芯片的背表面上来形成芯片堆叠。 引线框架上的芯片和引线之间的电连接通过将芯片上的有效表面上的焊盘和通过芯片延伸到后表面的通孔来实现。

公开(公告)号：US07495327B2

公开(公告)日：2009-02-24

申请号：US11606661

申请日：2006-11-29

申请人： Chen Jung Tsai ,  Chih Wen Lin

发明人： Chen Jung Tsai ,  Chih Wen Lin

IPC分类号： H01L23/495 ,  H01L23/02

CPC分类号： H01L23/49575 ,  H01L2224/13025 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2224/05599

摘要： An efficient chip stacking structure is described that includes a leadframe having two surfaces to each of which can be attached stacks of chips. A chip stack can be formed by placing a chip active surface on a back surface of another chip. Electrical connections between chips and leads on the leadframe are facilitated by bonding pads on chip active surfaces and by via that extend from the bonding pads through the chips to the back surfaces.

摘要翻译： 描述了一种有效的芯片堆叠结构，其包括具有两个表面的引线框架，其中每一个可以附接芯片堆叠。 可以通过将芯片有源表面放置在另一芯片的背表面上来形成芯片堆叠。 引线框架上的芯片和引线之间的电连接通过将芯片上的有效表面上的焊盘和通过芯片延伸到后表面的通孔来实现。