公开(公告)号：US07235838B2

公开(公告)日：2007-06-26

申请号：US10881372

申请日：2004-06-30

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee

IPC: H01L27/108

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10835 ,  H01L27/10858 ,  H01L27/10861 ,  H01L27/1203 ,  H01L28/55 ,  H01L28/82

Abstract: A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.

Abstract translation: 一种用于形成半导体器件的方法，该半导体器件包括具有嵌入式电容器结构的绝缘体上硅（SOI）衬底的DRAM单元结构，包括提供包括上覆的第一电绝缘层的衬底; 在所述第一电绝缘层上形成第一导电层以形成第一电极; 在所述第一电极上形成电容器电介质层; 在所述电容器介电层上形成第二导电层以形成第二电极; 在所述第二电极上形成第二电绝缘层; 以及在所述第二电极上形成单晶硅层以形成包括第一电容器结构的SOI衬底。

公开(公告)号：US07175709B2

公开(公告)日：2007-02-13

申请号：US10847099

申请日：2004-05-17

Applicant: Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

Inventor： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

IPC: C30B25/04

CPC classification number: C30B25/00 ,  C30B29/06 ,  C30B29/52 ,  Y10S438/933

Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

Abstract translation: 提供了形成均匀厚度的外延层的方法以改善表面平坦度。 首先提供衬底，然后通过外延在衬底上形成Si基层。 通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

公开(公告)号：US20060286740A1

公开(公告)日：2006-12-21

申请号：US11467980

申请日：2006-08-29

Applicant: Chun-Chieh LIN ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

Inventor： Chun-Chieh LIN ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

IPC: H01L21/8238 ,  H01L29/76

CPC classification number: H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78648

Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.

Abstract translation: 提供一种半导体器件及其制造方法。 该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。 第一硅化物可能与第二硅化物不同。 第一硅化物和第二硅化物可以是合金硅化物。

公开(公告)号：US06963114B2

公开(公告)日：2005-11-08

申请号：US10749273

申请日：2003-12-29

Applicant: Chun-Chieh Lin

Inventor： Chun-Chieh Lin

IPC: H01L29/41 ,  H01L21/02 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/785 ,  H01L27/1203 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66795 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A microelectronic device including an insulator located over a substrate, a semiconductor feature and a contact layer. The semiconductor feature has a thickness over the insulator, a first surface opposite the insulator, and a sidewall spanning at least a portion of the thickness. The contact layer has a first member extending over at least a portion of the first surface and a second member spanning at least a portion of the sidewall.

Abstract translation: 包括位于衬底上的绝缘体，半导体特征和接触层的微电子器件。 半导体特征具有超过绝缘体的厚度，与绝缘体相对的第一表面和横跨至少一部分厚度的侧壁。 接触层具有在第一表面的至少一部分上延伸的第一构件和跨越侧壁的至少一部分的第二构件。

公开(公告)号：US20050158923A1

公开(公告)日：2005-07-21

申请号：US11081104

申请日：2005-03-15

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L29/45 ,  H01L29/68 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/78618 ,  H01L29/78654

Abstract: A semiconductor device (100), including a dielectric pedestal (220) located above and integral to a substrate (110) and having first sidewalls (230), a channel region (210) located above the dielectric pedestal (220) and having second sidewalls (240), and source and drain regions (410) opposing the channel region (210) and each substantially spanning one of the second sidewalls (240). An integrated circuit (800) incorporating the semiconductor device (100) is also disclosed, as well as a method of manufacturing the semiconductor device (100).

Abstract translation: 一种半导体器件（100），包括位于衬底（110）上方并与衬底（110）成一体并具有第一侧壁（230）的电介质基座（220），位于电介质基座（220）上方的通道区域（210） （240），以及与沟道区（210）相对并且每个基本跨越第二侧壁（240）中的一个的源极和漏极区（410）。 还公开了结合半导体器件（100）的集成电路（800），以及制造半导体器件（100）的方法。

公开(公告)号：US20050127400A1

公开(公告)日：2005-06-16

申请号：US10745831

申请日：2003-12-24

Applicant: Yee-Chia Yeo ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Chung-Hu Ke ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Chung-Hu Ke ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L27/06 ,  H01L29/02 ,  H01L29/165 ,  H01L29/8605 ,  H01L31/109

CPC classification number: H01L27/0629 ,  H01L29/165 ,  H01L29/8605

Abstract: A heterostructure resistor comprises a doped region formed in a portion of a semiconductor substrate, the substrate comprising a first semiconductor material having a first natural lattice constant. The doped region comprises a semiconductor layer overlying the semiconductor substrate. The semiconductor layer comprises a second semiconductor material with a second natural lattice constant.

Abstract translation: 异质结构电阻器包括形成在半导体衬底的一部分中的掺杂区域，该衬底包括具有第一自然晶格常数的第一半导体材料。 掺杂区域包括覆盖半导体衬底的半导体层。 半导体层包括具有第二自然晶格常数的第二半导体材料。

公开(公告)号：US20050045965A1

公开(公告)日：2005-03-03

申请号：US10831021

申请日：2004-04-23

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/43 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78648

Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.

Abstract translation: 提供一种半导体器件及其制造方法。 该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。 第一硅化物可能与第二硅化物不同。 第一硅化物和第二硅化物可以是合金硅化物。

公开(公告)号：US20050035345A1

公开(公告)日：2005-02-17

申请号：US10832020

申请日：2004-04-26

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liang Yang ,  Yee-Chia Yeo

IPC: H01L21/28 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/06

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: An integrated circuit includes a substrate, a first transistor, and a second transistor. The first transistor has a first gate dielectric portion located between a first gate electrode and the substrate. The first gate dielectric portion includes a first high-permittivity dielectric material and/or a second high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. The second transistor has a second gate dielectric portion located between a second gate electrode and the substrate. The second gate dielectric portion includes the first high-permittivity dielectric material and/or the second high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness may be different than the first equivalent silicon oxide thickness.

Abstract translation: 集成电路包括衬底，第一晶体管和第二晶体管。 第一晶体管具有位于第一栅电极和衬底之间的第一栅电介质部分。 第一栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 第二晶体管具有位于第二栅电极和衬底之间的第二栅介质部分。 第二栅介质部分包括第一高介电常数电介质材料和/或第二高介电常数介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度可以不同于第一等效氧化硅厚度。

公开(公告)号：US06288265B1

公开(公告)日：2001-09-11

申请号：US09399879

申请日：1999-09-20

Applicant: Jih Ru Hwu ,  Shwu-Chen Tsay ,  Gholam H. Hakimelahi ,  Chun Chieh Lin ,  Wen Nan Tseng ,  Ali A. Moshfegh ,  Abdolmajid Azaripour ,  Hasan Mottaghian

Inventor： Jih Ru Hwu ,  Shwu-Chen Tsay ,  Gholam H. Hakimelahi ,  Chun Chieh Lin ,  Wen Nan Tseng ,  Ali A. Moshfegh ,  Abdolmajid Azaripour ,  Hasan Mottaghian

IPC: C07C6976

CPC classification number: C07D501/00

Abstract: A series of phloroglucide derivatives are synthesized, which possess potent antibacterial activities. They include unsymmetrical phloroglucide analogs, phloroglucides attached to cephalosporins at the C-3′ position, and 7-(phloroglucidamido)cephalosporins.

Abstract translation: 合成了一系列具有强力抗菌活性的花生四烯衍生物。 它们包括不对称的间苯三酚类似物，在C-3'位置连接到头孢菌素的间苯三酚和7-（间苯三酰胺）头孢菌素。

公开(公告)号：US5734032A

公开(公告)日：1998-03-31

申请号：US581314

申请日：1995-12-29

Applicant: Jih Ru Hwu ,  Shwu-Chen Tsay ,  Buh-Luen Chen ,  Himatkumar V. Patel ,  Wan-Lin Chen ,  Chun Chieh Lin ,  Ching-Tai Chou

Inventor： Jih Ru Hwu ,  Shwu-Chen Tsay ,  Buh-Luen Chen ,  Himatkumar V. Patel ,  Wan-Lin Chen ,  Chun Chieh Lin ,  Ching-Tai Chou

IPC: C07H21/00 ,  C12N15/10 ,  C12Q1/68 ,  C01B21/14

CPC classification number: C07H21/00 ,  C12N15/10 ,  C12Q1/68

Abstract: The present invention discloses a photo-induced DNA-cleaving agent composition comprises N-aryl-N-(alkyl or arylalkyl)hydroxylamine having the following formula: ##STR1## wherein R is C.sub.1 -C.sub.6 alkyl, phenyl, C.sub.1 -C.sub.6 alkoxy, phenoxy, C.sub.1 -C.sub.6 alkoxycarbonyl, halogen or halo(C.sub.1 -C.sub.6 alkyl)wherein R.sub.1 is hydrogen, C.sub.1 -C.sub.6 alkyl, phenyl, C.sub.1 -C.sub.6 alkoxy, C.sub.1 -C.sub.6 alkoxycarbonyl, halogen or halo(C.sub.1 -C.sub.6 alkyl); R.sub.2 is hydrogen; R.sub.3 is hydrogen or phenyl; R.sub.4 is hydrogen, phenyl, hydroxylphenyl, methoxyphenyl, dimethoxyphenyl, dimethylaminophenyl or naphthyl. The present N-aryl-N-(alkyl or arylalkyl)hydroxylamine is stable in dark, but it can react with O.sub.2 to form HO.multidot. radicals under irradiation of UV light for a period of 2-3 hours. The HO.multidot. radicals then react with DNA to accomplish cleavage of DNA.

Abstract translation: 本发明公开了一种光致DNA切割剂组合物，其包含具有下式的N-芳基-N-（烷基或芳烷基）羟胺：其中R是C1-C6烷基，苯基，C1-C6 烷氧基，苯氧基，C1-C6烷氧基羰基，卤素或卤素（C1-C6烷基），其中R1是氢，C1-C6烷基，苯基，C1-C6烷氧基，C1-C6烷氧基羰基，卤素或卤素（C1-C6烷基） R2是氢; R3是氢或苯基; R4是氢，苯基，羟基苯基，甲氧基苯基，二甲氧基苯基，二甲基氨基苯基或萘基。 本发明的N-芳基-N-（烷基或芳基烷基）羟胺在黑暗中稳定，但在紫外线照射下可与O 2反应形成HOx自由基2-3小时。 然后，HOx自由基与DNA反应以完成DNA的切割。