公开(公告)号：US5734554A

公开(公告)日：1998-03-31

申请号：US671310

申请日：1996-07-01

申请人： Nagaraj P. Mitty ,  Herbert E. LeCornu ,  Deviprasad Malladi

发明人： Nagaraj P. Mitty ,  Herbert E. LeCornu ,  Deviprasad Malladi

IPC分类号： H01L23/467 ,  H05K7/20

CPC分类号： H01L23/467 ,  H01L2924/0002

摘要： Because of space limitations, a small heat sink and a fan (of about 2".times.2".times.1/2" size) is used to cool to below 105.degree. C. (at an ambient temperature of about 40.degree. C.) a CPU chip (of about 16 mm.times.16 mm size) which uses about 30 watts current and is mounted on a motherboard of considerably larger size. A heat transferring thermostrate washer covers the chip and a pad covers the washer. Soldered to the pad is a square heat slug. Studs extend upward from the slug. The studs fit through holes in the base of the heat sink. The heat sink is of the type having plural rectangular cross-section fins extending upwardly from the base. Above the heat sink is a fan attached to the motherboard by screws at its four corners extending through heat slug and into the motherboard.

摘要翻译： 由于空间限制，使用小的散热器和风扇（约2'x2''x + E，fra 1/2 + EE“尺寸）冷却至低于105℃（在环境温度 约40℃）的CPU芯片（约16mm×16mm尺寸），其使用约30瓦特电流并且安装在具有相当大尺寸的主板上。 传热热垫片垫圈覆盖芯片，衬垫覆盖垫圈。 焊接到垫是一个方形的热塞。 螺柱从s extend向上延伸。 螺柱通过散热器底座上的孔安装。 散热器具有从基座向上延伸的多个矩形横截面翅片的类型。 在散热片上方的风扇是通过螺丝连接在主板上的风扇，其四个角部延伸穿过热塞并进入主板。

公开(公告)号：US5629240A

公开(公告)日：1997-05-13

申请号：US462400

申请日：1995-06-05

申请人： Deviprasad Malladi ,  Shahid S. Ansari ,  Eric Bogatin

发明人： Deviprasad Malladi ,  Shahid S. Ansari ,  Eric Bogatin

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/50 ,  H01L23/528 ,  H01L23/64 ,  H01L25/16 ,  H01L21/60

CPC分类号： H01L23/642 ,  H01L23/50 ,  H01L23/5286 ,  H01L24/49 ,  H01L25/16 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4911 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011

摘要： Switching noise at integrated circuit V.sub.DD and V.sub.SS metal traces is reduced by minimizing lead inductance in on-chip bypass capacitors. For each on-chip bypass capacitor, a pair of V.sub.DD -carrying and V.sub.SS -carrying metal traces is formed, these traces having regions spaced-apart laterally a distance .DELTA.X corresponding to lateral separation of the bypass capacitor connecting pads. For each bypass capacitor, column-shaped openings, spaced-apart distance .DELTA.X, are formed through the passivation and inter-metal oxide layers, as needed. These openings expose and access regions of the pair of spaced-apart metal traces carrying V.sub.SS and V.sub.DD. These openings, which may be formed after the IC has been fabricated, preferably are formed using focussed ion beam technology ("FIB"). Alternatively, these openings may be formed using masking and etching steps. The column-shaped openings are then made into conductive columnar elements, preferably using FIB deposition of tungsten or platinum. Conductive element pads are formed atop the conductive columnar elements at the outer surface of the IC passivation layer. The bypass capacitors are then attached to the IC, and the capacitor connecting pads are electrically connected to the respective conductive element pads using conductive epoxy or solder. This direct attachment of the on-chip bypass capacitors reduces effective capacitance lead inductance and improves attenuation of on-chip switching noise.

摘要翻译： 通过最小化片上旁路电容的引线电感，降低集成电路VDD和VSS金属走线的开关噪声。 对于每个片上旁路电容器，形成一对带VDD和VSS的金属迹线，这些迹线具有横向间隔开的距离为对应于旁路电容器连接焊盘的横向分离的距离DELTA X的区域。 对于每个旁路电容器，根据需要通过钝化和金属间氧化物层形成间隔开的距离DELTA X的柱状开口。 这些开口暴露并接近承载VSS和VDD的一对间隔开的金属迹线的区域。 可以在IC制造之后形成的这些开口优选地使用聚焦离子束技术（“FIB”）形成。 或者，这些开口可以使用掩模和蚀刻步骤形成。 然后将柱状开口制成导电柱状元件，优选使用FIB沉积钨或铂。 导电元件焊盘形成在IC钝化层的外表面上的导电柱状元件顶上。 然后将旁路电容器连接到IC，并且使用导电环氧树脂或焊料将电容器连接焊盘电连接到相应的导电元件焊盘。 片上旁路电容器的直接连接降低了有效的电容引线电感，并改善了片上开关噪声的衰减。

公开(公告)号：US5598035A

公开(公告)日：1997-01-28

申请号：US639721

申请日：1996-04-29

申请人： Stefan Rusu ,  Clayton L. Yee ,  Deviprasad Malladi ,  Alan C. Rogers

发明人： Stefan Rusu ,  Clayton L. Yee ,  Deviprasad Malladi ,  Alan C. Rogers

IPC分类号： H01L25/00 ,  H01L23/498 ,  H01L25/16 ,  H01L23/34

CPC分类号： H01L23/498 ,  H01L23/49838 ,  H01L25/165 ,  H01L2924/0002

摘要： A package for an integrated circuit is described. The package houses an integrated circuit with a signal quality sensitive integrated circuit element, such as a voltage controlled oscillator of a phase-locked loop. A package-mounted storage capacitor is positioned on the package body to generate a precision control signal. A signal path is constructed between the package-mounted storage capacitor and the integrated circuit to route the precision control signal to the integrated circuit. The relatively short signal path from the package-mounted storage capacitor to the integrated circuit has reduced parasitic capacitance, inductance, and resistance to maintain the quality of the precision control signal. To improve signal quality, certain portions of the signal path are electrically isolated with a shielding trace.

摘要翻译： 描述了用于集成电路的封装。 该封装包含一个具有信号质量敏感的集成电路元件的集成电路，例如锁相环的压控振荡器。 封装安装的存储电容器位于封装主体上以产生精确控制信号。 在封装安装的存储电容器和集成电路之间构建信号路径，以将精密控制信号路由到集成电路。 从封装安装的存储电容器到集成电路的相对短的信号路径减小了寄生电容，电感和电阻，以保持精度控制信号的质量。 为了提高信号质量，信号路径的某些部分与屏蔽迹线电隔离。

公开(公告)号：US20110256925A1

公开(公告)日：2011-10-20

申请号：US13014991

申请日：2011-01-27

申请人： John Schipani ,  Deviprasad Malladi

发明人： John Schipani ,  Deviprasad Malladi

IPC分类号： A63F9/24

CPC分类号： G07F17/3269 ,  G06Q50/34 ,  G07F17/32 ,  G07F17/3288

摘要： Methods, systems, and software for accepting bets on contests, such as sporting events, with wagering terms that change in real-time with the progress of the contests are disclosed. The disclosed methods, systems, and software may include security features that check the time at which bets are placed to ensure that they are not being placed in the interval between when an event occurred in the contest and when the wagering terms were changed to reflect that the event occurred.

摘要翻译： 公开了用于接受竞赛投注的方法，系统和软件，例如体育赛事，具有随比赛进度实时变化的下注条件。 公开的方法，系统和软件可以包括检查投注时间的安全特征，以确保它们不被放置在比赛中发生事件之间的时间间隔和当投注条件被改变以反映 事件发生了。

公开(公告)号：US06351389B1

公开(公告)日：2002-02-26

申请号：US08646426

申请日：1996-05-07

申请人： Deviprasad Malladi

发明人： Deviprasad Malladi

IPC分类号： H05K118

CPC分类号： H01L23/10 ,  H01L21/563 ,  H01L23/24 ,  H01L23/49822 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

摘要： A method and apparatus for packaging an electronic device, such as an integrated circuit chip (8), includes an intermediate device carrier (6) with a substantially planar upper surface (16) and a plurality of bonding pads (18) for coupling the carrier to the integrated circuit chip. A ceramic ring (38) is attached to the upper surface of the device carrier and a thermally conductive cover plate (36) is attached to the ceramic ring to form an inner cavity for receiving the chip therein. The ceramic ring comprises a material with a coefficient of thermal expansion substantially similar to or as the same as the device carrier to minimize stress therebetween during thermal expansion or contraction of the package device. The thermally conductive cover plate provides a path for dissipating heat generated during electrical operations of the chip.

摘要翻译： 用于封装诸如集成电路芯片（8）的电子器件的方法和装置包括具有基本平坦的上表面（16）的中间器件载体（6）和用于将载体 到集成电路芯片。 陶瓷环（38）附着到器件载体的上表面，并且导热盖板（36）附接到陶瓷环上以形成用于在其中接收芯片的内腔。 陶瓷环包括具有与装置载体基本相似或相同的热膨胀系数的材料，以在包装装置的热膨胀或收缩期间最小化其间的应力。 导热盖板提供用于耗散芯片的电气操作期间产生的热量的路径。

公开(公告)号：US06246252B1

公开(公告)日：2001-06-12

申请号：US09364563

申请日：1999-07-30

申请人： Deviprasad Malladi ,  Shahid Ansari ,  Hanxi Chen ,  Bidyut Sen ,  Steven Boyle

发明人： Deviprasad Malladi ,  Shahid Ansari ,  Hanxi Chen ,  Bidyut Sen ,  Steven Boyle

IPC分类号： G01R3126

CPC分类号： G01R1/0408 ,  H01L2224/73204 ,  H01L2924/15311

摘要： A method for providing for electrical testing of an integrated semiconductor substrate having at least two signal processing layers. The substrate may be provided with a protective layer of plastic, silicon, silicon oxide, silicon nitride or the like. A selected region of one substrate layer to be tested electrically is exposed by etching or otherwise forming a controllably small aperture any overlying substrate layer(s) away to expose at least one selected circuit trace in the selected region and applying a selected electrical signal to the trace. Optionally, a second aperture, spaced apart from the first aperture, can be formed to expose a second selected circuit trace so that propagation of a signal in one or more substrate circuits can be tested. The aperture cross-sectional shapes may be linear or curvilinear polygons or other suitable shapes.

摘要翻译： 一种用于提供具有至少两个信号处理层的集成半导体衬底的电测试的方法。 衬底可以设置有塑料，硅，氧化硅，氮化硅等的保护层。 待电测试的一个衬底层的选定区域通过蚀刻或以其它方式形成任何覆盖的衬底层的可控制的小孔而露出，以暴露所选区域中的至少一个选择的电路迹线，并将选择的电信号施加到 跟踪。 可选地，可以形成与第一孔间隔开的第二孔，以暴露第二选择的电路迹线，从而可以测试一个或多个衬底电路中的信号传播。 孔径横截面形状可以是线性或曲线多边形或其它合适的形状。

公开(公告)号：US08283204B2

公开(公告)日：2012-10-09

申请号：US13075803

申请日：2011-03-30

申请人： Vadim Gektin ,  Deviprasad Malladi

发明人： Vadim Gektin ,  Deviprasad Malladi

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/42 ,  H01L23/4275 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/16195

摘要： A multi-surface compliant heat removal process that includes identifying components to share a heat rejecting device; applying non-adhesive film to the components; identifying a primary component of the components; and applying phase change material on each of the components, other than the primary component. The phase change material is placed on top of the non-adhesive film. The process also includes placing the heat rejecting device on the corresponding components and removing the heat rejecting device from the corresponding components. The phase change material and the non-adhesive film remain with the heat rejecting device. The process also includes reflowing the phase change material on the heat rejecting device; removing the non-adhesive film from the heat rejecting device; placing a heatsink-attach thermal interface material on the components; and placing the heat rejecting device on the corresponding components.

摘要翻译： 一种多表面兼容的散热过程，其包括识别部件以共享散热装置; 将非粘合膜施加到部件上; 识别组件的主要组件; 并且将相变材料施加到除主要部件之外的每个部件上。 相变材料放置在非粘合膜的顶部。 该方法还包括将散热装置放置在相应的部件上，并从相应的部件移除散热装置。 相变材料和非粘合膜保留在散热装置上。 该方法还包括在排热装置上回流相变材料; 从散热装置中除去非粘合膜; 将散热片附着的热界面材料放置在部件上; 并将散热装置放置在相应的部件上。

公开(公告)号：US06944025B2

公开(公告)日：2005-09-13

申请号：US10644941

申请日：2003-08-19

申请人： David M. Hockanson ,  Ron Zhang ,  George Zacharisen ,  Deviprasad Malladi

发明人： David M. Hockanson ,  Ron Zhang ,  George Zacharisen ,  Deviprasad Malladi

IPC分类号： H01L23/40 ,  H01L23/552 ,  H05K7/20

CPC分类号： H01L23/4006 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electromagnetic shielding structure is provided for a microprocessor or other electronic device that emits electromagnetic radiation. The structure includes a heat sink with an integrally formed depending skirt, and a conductive, compressible polymer is applied to a bottom surface of the skirt. The bottom surface mounts against a socket carried on a circuit board and is electrically coupled to a ground plane of the circuit board. The socket substantially surrounds the microprocessor in at least two dimensions (e.g. length and width). A shielding structure is formed at least partly by the heat sink, the socket and the ground plane.

摘要翻译： 为微处理器或发射电磁辐射的其他电子设备提供电磁屏蔽结构。 该结构包括具有整体形成的悬垂裙部的散热器，并且将导电的可压缩聚合物施加到裙部的底部表面。 底表面安装在承载在电路板上的插座上，并且电耦合到电路板的接地平面。 插座基本上以至少两个维度（例如长度和宽度）包围微处理器。 至少部分地由散热器，插座和接地平面形成屏蔽结构。

公开(公告)号：US06727193B2

公开(公告)日：2004-04-27

申请号：US10093669

申请日：2002-03-08

申请人： Vadim Gektin ,  Deviprasad Malladi

发明人： Vadim Gektin ,  Deviprasad Malladi

IPC分类号： H01L2126

CPC分类号： H01L23/433 ,  H01L23/3735 ,  H01L29/51 ,  H01L2924/0002 ,  H01L2924/00

摘要： Novel methods and apparatus to enhance thermal performance of IC packages are disclosed. In an embodiment, a method of enhancing thermal uniformity across a semiconductor device is disclosed. The method includes providing the semiconductor device. The semiconductor device has a plurality of thermal regions. A first thermal region of the plurality of thermal regions has a different temperature than a second thermal region of the plurality of thermal regions. The method further provides a thermal enhancement material substantially adjacent to the first and second thermal regions. In another embodiment, a thermal conductivity of the thermal enhancement material is adjusted in relation to a temperature effecting the thermal enhancement material.

摘要翻译： 公开了提高IC封装热性能的新方法和装置。 在一个实施例中，公开了一种提高半导体器件的热均匀性的方法。 该方法包括提供半导体器件。 半导体器件具有多个热区域。 多个热区域的第一热区域具有与多个热区域中的第二热区域不同的温度。 该方法还提供了基本上与第一和第二热区域相邻的热增强材料。 在另一个实施例中，相对于影响热增强材料的温度调节热增强材料的热导率。

公开(公告)号：US06637506B2

公开(公告)日：2003-10-28

申请号：US10093643

申请日：2002-03-08

申请人： Vadim Gektin ,  Deviprasad Malladi

发明人： Vadim Gektin ,  Deviprasad Malladi

IPC分类号： H05K720

CPC分类号： F28F23/00 ,  F28F2013/006 ,  H01L23/433 ,  H01L24/32 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/00

摘要： In an embodiment, an apparatus for enhancing a thermal match between portions of a semiconductor device is disclosed. The apparatus includes a die and a heat spreader. The heat spreader is in thermal contact with the die. The heat spreader has a center portion and a perimeter portion. The center portion and the perimeter portions are structurally coupled to each other. In another embodiment, the perimeter portion of the heat spreader is selected from material with a lower CTE than the material for the center portion of the heat spreader.

摘要翻译： 在一个实施例中，公开了一种用于增强半导体器件的部分之间的热匹配的装置。 该装置包括模具和散热器。 散热器与模具热接触。 散热器具有中心部分和周边部分。 中心部分和周边部分在结构上彼此耦合。 在另一个实施例中，散热器的周边部分选自具有比散热器的中心部分的材料更低的CTE的材料。