公开(公告)号：US07439198B2

公开(公告)日：2008-10-21

申请号：US11153239

申请日：2005-06-15

Applicant: Hans-Joachim Schulze ,  Helmut Strack

Inventor： Hans-Joachim Schulze ,  Helmut Strack

IPC: H01L21/00

CPC classification number: H01L29/7802 ,  H01L21/3221 ,  H01L29/1095 ,  H01L29/40 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/66712 ,  H01L29/7395

Abstract: A method for fabricating a buried metallic layer at a predetermined vertical position in a semiconductor body having a first and second side includes a step of applying a metal layer to one of the first and second sides at least in sections. The method also includes establishing a positive temperature gradient in a vertical direction of the semiconductor body proceeding from the one side. The temperature in the region of the one side is higher than the eutectic temperatures of system, so that the metal of the metal layer migrates in the vertical direction into the semiconductor body. The method also includes discontinuing the temperature gradient once the metal reaches the predetermined vertical position in the semiconductor body, in order thereby to obtain the metallic layer at the predetermined position.

Abstract translation: 在具有第一和第二侧面的半导体本体中，在预定垂直位置处制造掩埋金属层的方法包括至少部分地将金属层施加到第一和第二侧中的一个的步骤。 该方法还包括在从一侧进行的半导体本体的垂直方向上建立正温度梯度。 一侧区域的温度高于系统的共晶温度，金属层的金属沿垂直方向移动到半导体本体内。 该方法还包括一旦金属达到半导体本体中的预定垂直位置就停止温度梯度，从而在预定位置获得金属层。

公开(公告)号：US07317252B2

公开(公告)日：2008-01-08

申请号：US10686849

申请日：2003-10-16

Applicant: Anton Mauder ,  Hans-Joachim Schulze ,  Helmut Strack

Inventor： Anton Mauder ,  Hans-Joachim Schulze ,  Helmut Strack

IPC: H01L23/48

CPC classification number: H01L29/7802 ,  H01L29/1604 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/7396 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A contact configuration has an ohmic contact between a metalization layer and a semiconductor body of monocrystalline semiconductor material. An amorphous semiconductor layer is formed between the metalization layer and the monocrystalline semiconductor body. The layer is formed of the same semiconductor material as the body. The contact configuration is either produced by applying amorphous semiconductor material on the semiconductor body (e.g., sputtering, vapor deposition, glow discharge) or by damage formation in the semiconductor body.

Abstract translation: 接触构造在金属化层和单晶半导体材料的半导体本体之间具有欧姆接触。 在金属化层和单晶半导体本体之间形成非晶半导体层。 该层由与本体相同的半导体材料形成。 接触构造是通过在半导体本体上施加非晶半导体材料（例如溅射，气相沉积，辉光放电）或通过半导体本体中的损伤形成来制造的。

公开(公告)号：US20070148422A1

公开(公告)日：2007-06-28

申请号：US11613253

申请日：2006-12-20

Applicant: Hans-Joachim Schulze ,  Helmut Strack

Inventor： Hans-Joachim Schulze ,  Helmut Strack

IPC: B32B3/00

CPC classification number: H01L29/7802 ,  H01L29/41741 ,  H01L29/456 ,  H01L29/66712 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19043 ,  Y10T428/24917 ,  H01L2924/00

Abstract: In a semiconductor wafer substrate (20) for power semiconductor components (1) and in a method for producing the same, the semiconductor wafer substrate (20) has a large-area, buried rear side electrode (3) in form of a layer arranged between a self-supporting wafer substrate (4) and a non-self-supporting monocrystalline silicon wafer layer (5) arranged on the rear side electrode (3). The rear side electrode (3) has a ternary carbide and/or a ternary nitride and/or carbon.

Abstract translation: 在用于功率半导体部件（1）的半导体晶片基板（20）中及其制造方法中，半导体晶片基板（20）具有大面积埋入式的背面侧电极（3） 在自支撑晶片基板（4）和布置在后侧电极（3）上的非自支撑单晶硅晶片层（5）之间。 后侧电极（3）具有三元碳化物和/或三元氮化物和/或碳。

公开(公告)号：US20070023881A1

公开(公告)日：2007-02-01

申请号：US11427204

申请日：2006-06-28

Applicant: Helmut Strack

Inventor： Helmut Strack

IPC: H01L23/02 ,  H01L21/00

CPC classification number: H01L21/6835 ,  H01L21/76256 ,  H01L21/76834 ,  H01L21/76838 ,  H01L29/417 ,  H01L29/456 ,  H01L29/861 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68363 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00

Abstract: A semiconductor wafer is provided with a wiring structure, and semiconductor chip positions arranged in rows and columns. The semiconductor wafer has at least one coating (6) as a self-supporting dimensionally stable substrate layer (4), and/or as a wiring structure composed of conductive, high-temperature-resistant material. The coating material (6) of the substrate layer (4) and/or of the wiring structure has a ternary carbide and/or a ternary nitride and/or carbon.

Abstract translation: 半导体晶片设置有布线结构，半导体芯片位置配置成行和列。 半导体晶片具有至少一个作为自支撑尺寸稳定的基板层（4）的涂层（6），和/或作为由导电的耐高温材料构成的布线结构。 衬底层（4）和/或布线结构的涂层材料（6）具有三元碳化物和/或三元氮化物和/或碳。

公开(公告)号：US20060180932A1

公开(公告)日：2006-08-17

申请号：US11328595

申请日：2006-01-10

Applicant: Ralf Otremba ,  Khalil Hosseini ,  Helmut Strack

Inventor： Ralf Otremba ,  Khalil Hosseini ,  Helmut Strack

IPC: H01L23/52

CPC classification number: H01L24/72 ,  H01L23/051 ,  H01L23/4334 ,  H01L23/49562 ,  H01L24/48 ,  H01L25/117 ,  H01L2224/48472 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One embodiment of the invention relates to a component arrangement having a semiconductor chip, a chip carrier, a contact piece and a package. The semiconductor chip includes a first load terminal, a second load terminal and a control terminal, with the first load terminal and the second load terminal being arranged on mutually opposite sides of the semiconductor chip. The semiconductor chip is arranged on the chip carrier and is electrically and thermally conductively connected to the first load terminal. The contact piece is arranged on the second load terminal and is electrically and thermally conductively connected to it. The package is formed from a dielectric compound, which surrounds the semiconductor chip, the chip carrier and the contact piece. The chip carrier is exposed on a first side of the package, the contact piece is exposed on a second side of the package opposite the first side. A connecting leg is passed out of the package and is electrically conductively connected to the control terminal. One embodiment of the invention furthermore relates to a component cascade, in which a plurality of component arrangements are arranged on one another in the form of a stack.

Abstract translation: 本发明的一个实施例涉及具有半导体芯片，芯片载体，接触片和封装的部件布置。 半导体芯片包括第一负载端子，第二负载端子和控制端子，其中第一负载端子和第二负载端子布置在半导体芯片的相对的相对侧上。 半导体芯片布置在芯片载体上并且电和热导电地连接到第一负载端子。 接触件布置在第二负载端子上，并且与导电连接。 封装由围绕半导体芯片，芯片载体和接触片的电介质化合物形成。 芯片载体暴露在封装的第一侧上，接触件暴露在与第一侧相对的封装的第二侧上。 连接腿从包装件中流出并与导电连接到控制端子。 本发明的一个实施例还涉及一种组件级联，其中多个组件布置以堆叠的形式彼此布置。

公开(公告)号：US06828609B2

公开(公告)日：2004-12-07

申请号：US10455834

申请日：2003-06-06

Applicant: Gerald Deboy ,  Dirk Ahlers ,  Helmut Strack ,  Michael Rueb ,  Hans Martin Weber

Inventor： Gerald Deboy ,  Dirk Ahlers ,  Helmut Strack ,  Michael Rueb ,  Hans Martin Weber

IPC: H01L2980

CPC classification number: H01L29/7816 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7801 ,  H01L29/7802

Abstract: A semiconductor component having a semiconductor body comprises a blocking pn junction, a source zone of a first conductivity type and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type. The side of the zone of the second conductivity type faces the drain zone forming a first surface, and in the region between the first surface and a second surface areas of the first and second conductivity type are nested in one another. The areas of the first and second conductivity type are variably so doped that near the first surface doping atoms of the second conductivity type predominate, and near the second surface doping atoms of the first conductivity type predominate. Furthermore a plurality of floating zones of the first and second conductivity type is provided.

Abstract translation: 具有半导体主体的半导体部件包括阻挡pn结，第一导电类型的源极区域，并且与形成与第一导电类型互补的第二导电类型的阻挡pn结的区域接合，并且第一导电类型的漏极区域 导电类型。 第二导电类型的区域侧面对排水区，形成第一表面，并且在第一表面和第一和第二导电类型的第二表面区域之间的区域彼此嵌套。 第一和第二导电类型的区域是可变地掺杂的，在第一表面附近，第二导电类型的掺杂原子占主导地位，并且在第二表面附近，第一导电类型的掺杂原子占主导地位。 此外，提供了第一和第二导电类型的多个浮动区域。

公开(公告)号：US06812524B2

公开(公告)日：2004-11-02

申请号：US10013999

申请日：2001-12-11

Applicant: Dirk Ahlers ,  Jens-Peer Stengl ,  Jenoe Tihanyi ,  Hans Weber ,  Gerald Deboy ,  Helmut Strack ,  Armin Willmeroth

Inventor： Dirk Ahlers ,  Jens-Peer Stengl ,  Jenoe Tihanyi ,  Hans Weber ,  Gerald Deboy ,  Helmut Strack ,  Armin Willmeroth

IPC: H01L2976

CPC classification number: H01L29/7802 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/7816

Abstract: A semiconductor component includes first and second connection zones formed in a semiconductor body, a channel zone surrounding the second connection zone in the semiconductor body, and a drift path that is formed between the channel zone and the first connection zone and contains a compensation zone. The compensation zone has a complementary conduction type with respect to the drift zone and includes at least two segments. A distance between the two adjacent segments is chosen such that the punch-through voltage between these segments lies in a voltage range that corresponds to the voltage range assumed by the voltage drop across the drift path at currents situated between the rated current and twice the rated current.

Abstract translation: 半导体部件包括形成在半导体本体中的第一和第二连接区域，围绕半导体主体中的第二连接区域的沟道区域以及形成在沟道区域和第一连接区域之间并且包含补偿区域的漂移路径。 补偿区相对于漂移区具有互补导电类型并且包括至少两个段。 选择两个相邻段之间的距离，使得这些段之间的穿通电压位于对应于位于额定电流和额定电流两倍之间的电流处的漂移路径上的电压降所假定的电压范围的电压范围 当前。

公开(公告)号：US06649459B2

公开(公告)日：2003-11-18

申请号：US09817594

申请日：2001-03-26

Applicant: Gerald Deboy ,  Wolfgang Friza ,  Oliver Häberlen ,  Michael Rüb ,  Helmut Strack

Inventor： Gerald Deboy ,  Wolfgang Friza ,  Oliver Häberlen ,  Michael Rüb ,  Helmut Strack

IPC: H01L21338

CPC classification number: H01L29/7802 ,  H01L21/26586 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/41766

Abstract: The invention relates to a method for producing a semiconductor component including semiconductor areas of different conductivity types which are alternately positioned in a semiconductor body. The semiconductor areas of different conductivity types extend at least from one first zone to a position near a second zone. Because of variable doping in trenches and in the trench fillings, an electric field is generated which increases from both the first zone and the second zone.

Abstract translation: 本发明涉及一种用于制造半导体元件的方法，该半导体元件包括交替地位于半导体本体中的不同导电类型的半导体区域。 不同导电类型的半导体区域至少从一个第一区延伸到靠近第二区的位置。 由于沟槽和沟槽填充中的可变掺杂，产生从第一区和第二区两者增加的电场。

公开(公告)号：US06225643B1

公开(公告)日：2001-05-01

申请号：US09158248

申请日：1998-09-22

Applicant: Jenoe Tihanyi ,  Helmut Strack

Inventor： Jenoe Tihanyi ,  Helmut Strack

IPC: H01L2904

CPC classification number: H01L29/7802 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/6634 ,  H01L29/7395 ,  H01L29/7396

Abstract: An SOI cell includes a semiconductor body having at least one insulator layer. A polycrystalline zone doped with a dopant of a first conductivity type is grown on the insulator layer. The polycrystalline zone is adjoined outside the region of the insulator layer by a semiconductor region, which is doped with the dopant of the first conduction type that has been diffused out of the polycrystalline zone. A dopant source having a dopant of a second conductivity type is also provided. A zone having the dopant of the second conductivity type is formed by diffusing the dopant out of the dopant source.

Abstract translation: SOI单元包括具有至少一个绝缘体层的半导体本体。 在绝缘体层上生长掺杂有第一导电类型的掺杂剂的多晶区。 多晶区域通过半导体区域与绝缘体层的区域相邻，该半导体区域掺杂有已经扩散到多晶区域的第一导电类型的掺杂剂。 还提供了具有第二导电类型的掺杂剂的掺杂剂源。 通过将掺杂剂从掺杂剂源扩散出来，形成具有第二导电类型的掺杂剂的区域。

公开(公告)号：US06184555B2

公开(公告)日：2001-02-06

申请号：US09117636

申请日：1998-12-04

Applicant: Jeno Tihanyi ,  Helmut Strack ,  Heinrich Geiger

Inventor： Jeno Tihanyi ,  Helmut Strack ,  Heinrich Geiger

IPC: H01L2976

CPC classification number: H01L29/7811 ,  H01L21/2257 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/66333 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7802 ,  H01L29/7835

Abstract: The invention relates to a field effect-controllable semiconductor component of vertical or lateral design i.e. MOSFETs and IGBTs. In this case, depletion zones and complementary depletion zones of opposite conduction types are introduced in the source-drain load path, in the semiconductor body, i.e. in the inner zone in the case of vertical components and in the drift zone in the case of lateral components, the concentration of the regions doped by the first conduction type corresponding approximately to the concentration of the regions doped by the second conduction type.

Abstract translation: 本发明涉及垂直或侧向设计的场效应可控半导体元件，即MOSFET和IGBT。 在这种情况下，相反导电类型的耗尽区和互补耗尽区被引入到半导体主体中的源极 - 漏极负载路径中，即在垂直分量的情况下在内部区域中，并且在横向 由第一导电类型掺杂的区域的浓度大致对应于由第二导电类型掺杂的区域的浓度。