Abstract:
A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern.
Abstract:
Provided are a home appliance and its system. The home appliance include: an input unit for inputting driving information; a data unit for storing a diagnosis logic; a control unit for diagnosing a state of the home appliance and whether a failure occurs according to the diagnosis logic on the basis of product information including the driving information inputted from the input unit, operation information detected during an operation, and failure information occurring during an operation, in order to generate a diagnosis result including the operation information and the failure information, and encoding transmission information including predetermined data for a diagnosis, which are selected from the driving operation, and the diagnosis result and outputting the encoded transmission information; a modulator for converting the encoded transmission information; and a sound output unit for outputting the transmission information converted by the modulator as a sound including a plurality of frequencies.
Abstract:
Provided are a home appliance and a method of outputting a signal sound for diagnosis. The home appliance includes: a selection unit for receiving a diagnosis command on the home appliance from a user; a memory for storing diagnosis data on the home appliance; a controller for processing the diagnosis data stored in the memory in order to generate a packet according to a diagnosis command input through the selection unit; a conversion unit for generating a frame including a combination of symbols, which respectively correspond to four different carrier frequencies, on the basis of data constituting the packet, according to a Quadrature Frequency Shift Keying (QFSK) method.
Abstract:
Subject matter disclosed herein relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly to a method of fabricating a phase change memory device.
Abstract:
By making an ovonic threshold switch using a carbon interfacial layer having a thickness of less than or equal to ten percent of the thickness of the associated electrode, cycle endurance may be improved. In some embodiments, a glue layer may be used between the carbon and the chalcogenide of the ovonic threshold switch. The glue layer may be effective to improve adherence between carbon and chalcogenide.
Abstract:
A small critical dimension element, such as a heater for an ovonic unified memory, may be formed within a pore by using successive sidewall spacers. The use of at least two successive spacers enables the limitations imposed by lithography and the limitations imposed by bread loafing to be overcome to provide reduced critical dimension elements.
Abstract:
The inventive concept relates to a semiconductor device and a method for fabricating the same. The semiconductor device comprises active patterns protruding from a substrate, an interlayer dielectric layer disposed on the substrate and including grooves exposing the active patterns, and gate electrodes in the grooves. The grooves include a first groove having a first width and a second groove having a second width greater than the first width. The gate electrodes include a first gate electrode in the first groove, and a second gate electrode in the second groove. Each of the first and second gate electrodes includes a first work function conductive pattern on a bottom surface and sidewalls of corresponding one of the first and second grooves, and a second work function conductive pattern on the first work function conductive pattern.
Abstract:
A storage device includes a nonvolatile memory device, a buffer memory, a controller and a neuromorphic chip. The neuromorphic chip is configured to generate an access classifier based on the access result information and the access environment information. The controller is configured to perform first accesses to the nonvolatile memory device using the buffer memory and to collects the access result information and the access environment information of the first accesses in the buffer memory. The controller is configured to perform a second access of the nonvolatile memory device using the buffer memory. The controller is configured to obtain a prediction result of access parameters associated with the second access by using access environment information associated with the second access and the access classifier.
Abstract:
By making an ovonic threshold switch using a carbon interfacial layer having a thickness of less than or equal to ten percent of the thickness of the associated electrode, cycle endurance may be improved. In some embodiments, a glue layer may be used between the carbon and the chalcogenide of the ovonic threshold switch. The glue layer may be effective to improve adherence between carbon and chalcogenide.
Abstract:
A method, device and system are provided for programming a flash memory device, the method including executing a bit line setup operation, and executing a channel pre-charge operation simultaneously with the bit line setup operation, the channel pre-charge operation including applying a channel pre-charge voltage to all word lines; and the device including a voltage generator disposed for providing each of a program voltage, a read voltage, a pass voltage, and a channel pre-charge voltage, a high-voltage switch connected to the voltage generator and disposed for switchably providing one of the program voltage, read voltage, pass voltage, or channel pre-charge voltage, and control logic connected to the high-voltage switch and disposed for simultaneously executing a bit line setup operation and a channel pre-charge operation, the channel pre-charge operation comprising controlling the high-voltage switch to apply the channel pre-charge voltage to both selected and unselected word lines of the device.