公开(公告)号：US08013438B2

公开(公告)日：2011-09-06

申请号：US12507049

申请日：2009-07-21

申请人： Jing-En Luan ,  Kum-Weng Loo

发明人： Jing-En Luan ,  Kum-Weng Loo

IPC分类号： H01L23/34

CPC分类号： H01L23/16 ,  H01L23/3121 ,  H01L23/36 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/16152 ,  H01L2924/19105

摘要： A semiconductor package includes a substrate board and a semiconductor die attached to a top surface of that substrate board. A heat spreader is provided over the semiconductor die. A stiffening ring is positioned surrounding the semiconductor die, the stiffening ring being attached to the top surface of the substrate board and attached to a bottom surface of the plate portion of the heat spreader. Space is left on the board outside of the stiffening ring to support the installation of passive components to the substrate board. An external ring may be included, with that external ring being interconnected to the stiffening ring by a set of tie bars. Alternatively, the heat spreader includes an integrally formed peripheral sidewall portion.

摘要翻译： 半导体封装包括衬底板和附接到该衬底板的顶表面的半导体管芯。 散热器设置在半导体管芯上。 加强环定位在半导体模具周围，加强环附接到基板的顶表面并且附接到散热器的板部分的底表面。 空间留在加强环外部的板上，以支持将无源部件安装到基板上。 可以包括外部环，该外环通过一组连接杆与加强环相互连接。 或者，散热器包括整体形成的外围侧壁部分。

公开(公告)号：US20100297813A1

公开(公告)日：2010-11-25

申请号：US12800639

申请日：2010-05-19

申请人： Kum-weng Loo ,  Chek-lim Kho ,  Jing-en Luan

发明人： Kum-weng Loo ,  Chek-lim Kho ,  Jing-en Luan

IPC分类号： H01L21/60 ,  H01L21/56

CPC分类号： H01L21/565 ,  H01L23/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.

摘要翻译： 本公开提供了一种非常薄的半导体封装，其包括具有管芯附接焊盘和多个引线端子的引线框架，附接到管芯附接焊盘并且通过接合线电连接到引线端子的管芯，位置构件设置在 模具和/或管芯附接垫，以及将引线框，模具和位置构件封装在一起以形成半导体封装的成型材料。 用于制造非常薄的半导体封装的方法包括在引线框的管芯安装焊盘的一侧上设置第一位置构件，将管芯附接到管芯附接衬垫的相对侧上，可选地将第二位置构件设置在顶部 的模具，将管芯电连接到引线框架的引线端子，并将引线框架，模具和位置构件封装在一起以形成非常薄的半导体封装。

公开(公告)号：US09640574B2

公开(公告)日：2017-05-02

申请号：US13029665

申请日：2011-02-17

申请人： Jing-En Luan ,  Junyong Chen

发明人： Jing-En Luan ,  Junyong Chen

IPC分类号： H01L27/146 ,  H04N5/225

CPC分类号： H01L27/14618 ,  H01L2224/48091 ,  H01L2224/73265 ,  H04N5/2253 ,  H04N5/2257 ,  H01L2924/00014

摘要： A process of forming optical sensors includes sealing an imaging portion of each of a plurality of optical sensors on a sensor wafer with a transparent material. The operation of sealing leaves a bonding portion of each of the optical sensors exposed. The process further includes cutting the wafer into a plurality of image sensor dies after sealing the optical sensors such that each image sensor die includes one of the optical sensors sealed with a corresponding portion of the transparent material.

公开(公告)号：US08389335B2

公开(公告)日：2013-03-05

申请号：US13424610

申请日：2012-03-20

申请人： Kim-Yong Goh ,  Jing-En Luan

发明人： Kim-Yong Goh ,  Jing-En Luan

IPC分类号： H01L21/00

CPC分类号： H01L23/367 ,  H01L23/04 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/0401

摘要： A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.

摘要翻译： 芯片级封装（CSP）器件包括具有电耦合到多个焊球的半导体管芯的CSP。 具有内顶表面和一个或多个侧壁的罐体限定了一个室。 CSP容纳在腔室中，并连接到罐的内部顶部表面。 印刷电路板附接到焊球和一个或多个侧壁以提供对CSP和罐的支撑。 CSP可能是晶片级CSP。 罐可以由金属物质或非金属物质制成。 在跌落测试期间和热循环测试期间，罐可以为CSP提供应力消除。

公开(公告)号：US20130009326A1

公开(公告)日：2013-01-10

申请号：US13605841

申请日：2012-09-06

申请人： Jing-en Luan

发明人： Jing-en Luan

IPC分类号： H01L23/488

CPC分类号： H01L23/3128 ,  H01L24/28 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package includes a substrate, an integrated circuit proximate a top surface of the substrate, and a cap comprising encapsulant that encapsulates the integrated circuit on at least a portion of the top surface of the substrate. The chip package further includes at least one extension feature positioned on at least a portion of the top surface of the substrate. The at least one extension feature also comprises the encapsulant and extends from the cap to a perimeter of the substrate.

摘要翻译： 芯片封装包括基板，靠近基板的顶表面的集成电路，以及包括将集成电路封装在基板的顶表面的至少一部分上的密封剂的盖。 芯片封装进一步包括位于衬底的顶表面的至少一部分上的至少一个延伸特征。 所述至少一个延伸部件还包括所述密封剂并且从所述盖延伸到所述基板的周边。

公开(公告)号：US08278146B2

公开(公告)日：2012-10-02

申请号：US12330143

申请日：2008-12-08

申请人： Jing-en Luan

发明人： Jing-en Luan

IPC分类号： H01L21/00 ,  H01L23/28 ,  H01L23/48 ,  H01L23/482 ,  H01L25/16

CPC分类号： H01L23/3128 ,  H01L24/28 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/078 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package includes a substrate, an integrated circuit proximate a top surface of the substrate, and a cap comprising encapsulant that encapsulates the integrated circuit on at least a portion of the top surface of the substrate. The chip package further includes at least one extension feature positioned on at least a portion of the top surface of the substrate. The at least one extension feature also comprises the encapsulant and extends from the cap to a perimeter of the substrate.

摘要翻译： 芯片封装包括基板，靠近基板的顶表面的集成电路，以及包括将集成电路封装在基板的顶表面的至少一部分上的密封剂的盖。 芯片封装进一步包括位于衬底的顶表面的至少一部分上的至少一个延伸特征。 所述至少一个延伸部件还包括所述密封剂并且从所述盖延伸到所述基板的周边。

公开(公告)号：US08164179B2

公开(公告)日：2012-04-24

申请号：US12336422

申请日：2008-12-16

申请人： Kim-Yong Goh ,  Jing-En Luan

发明人： Kim-Yong Goh ,  Jing-En Luan

IPC分类号： H01L23/12

CPC分类号： H01L23/367 ,  H01L23/04 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/0401

摘要： A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.

摘要翻译： 芯片级封装（CSP）器件包括具有电耦合到多个焊球的半导体管芯的CSP。 具有内顶表面和一个或多个侧壁的罐体限定了一个室。 CSP容纳在腔室中，并连接到罐的内部顶部表面。 印刷电路板附接到焊球和一个或多个侧壁以提供对CSP和罐的支撑。 CSP可能是晶片级CSP。 罐可以由金属物质或非金属物质制成。 在跌落测试期间和热循环测试期间，罐可以为CSP提供应力消除。

公开(公告)号：US20120074592A1

公开(公告)日：2012-03-29

申请号：US12893651

申请日：2010-09-29

申请人： Jing-En Luan

发明人： Jing-En Luan

IPC分类号： H01L23/48 ,  H01L21/56

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/12036 ,  H01L2924/14 ,  H01L2224/83 ,  H01L2224/19 ,  H01L2224/82 ,  H01L2924/00

摘要： An electronic package that includes a composite material base. In one embodiment the electronic package is an expanded wafer-level package. The composite material base is composed of woven strands and polymer material. In one embodiment the composite material base is composed of woven fiberglass strands and an epoxy material. In various embodiments the package includes an electronic circuitry layer on one or another face of the composite material base. In other embodiments conductive vias connect the circuitry layers, including a redistribution layer. In yet another embodiment an electronic package is mounted on the composite material base and electrically couples to the circuit of the expanded wafer-level package. The package having the composite material base is mechanically stronger and can be made thinner than a package that relies on an encapsulant material for structure, and resists cracking.

摘要翻译： 一种包括复合材料基底的电子封装。 在一个实施例中，电子封装是扩展的晶片级封装。 复合材料基底由编织线和聚合物材料组成。 在一个实施方案中，复合材料基底由编织的玻璃纤维束和环氧材料组成。 在各种实施例中，封装包括在复合材料基底的一个或另一个面上的电子电路层。 在其它实施例中，导电通孔连接电路层，包括再分配层。 在另一个实施例中，电子封装安装在复合材料基底上并电耦合到扩展的晶片级封装的电路。 具有复合材料基底的包装机械地更坚固，并且可以制成比依赖于用于结构的密封剂材料的包装，并且抗龟裂。

公开(公告)号：US20110156250A1

公开(公告)日：2011-06-30

申请号：US12651365

申请日：2009-12-31

申请人： Kim-Yong Goh ,  Jing-En Luan

发明人： Kim-Yong Goh ,  Jing-En Luan

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L21/565 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

摘要： A flip-chip fan-out wafer level package for package-on-package applications includes a semiconductor die with solder bumps on an upper surface in a flip chip configuration. The die is inverted, with an upper surface facing an upper side of a redistribution layer, with the solder bumps in electrical contact with respective chip contact pads of the redistribution layer. The redistribution layer includes conductive traces that place each of the solder bumps in electrical contact with one or both of one of a plurality of upper redistribution contact pads and one of a plurality of lower redistribution contact pads. Each of the plurality of upper redistribution contact pads has an upper solder ball in electrical contact therewith. The die and the upper solder balls are at least partially encapsulated in a layer of mold compound positioned on the upper surface of the redistribution layer, and whose lateral dimensions are defined by the lateral dimensions of the redistribution layer. The layer of mold compound has a back-ground surface at which a portion of each of the upper solder balls is exposed, for electrical contact with an upper package. Each of the lower redistribution contact pads has a lower solder ball a coupled thereto.

摘要翻译： 用于封装封装应用的倒装芯片扇出晶片级封装包括在倒装芯片配置的上表面上具有焊料凸块的半导体管芯。 模具倒置，上表面面向再分布层的上侧，焊料凸块与再分布层的相应芯片接触焊盘电接触。 再分配层包括导电迹线，其将每个焊料凸点与多个上再分布接触焊盘和多个下再分布接触焊盘之一中的一个或两者电接触。 多个上再分配接触垫中的每一个具有与其接触的上焊球。 模具和上焊球至少部分地封装在位于再分配层的上表面上的模具化合物层中，并且其横向尺寸由再分布层的横向尺寸限定。 模具化合物层具有背面表面，每个上焊球的一部分暴露在其中，用于与上封装电接触。 每个下再分布接触垫具有与其耦合的较低焊球。

公开(公告)号：US20070085177A1

公开(公告)日：2007-04-19

申请号：US11545814

申请日：2006-10-10

申请人： Kum-weng Loo ,  Chek-lim Kho ,  Jing-en Luan

发明人： Kum-weng Loo ,  Chek-lim Kho ,  Jing-en Luan

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L21/565 ,  H01L23/16 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present disclosure provides a very thin semiconductor package including a leadframe with a die-attach pad and a plurality of lead terminals, a die attached to the die-attach pad and electrically connected to the lead terminals via bonding wires, a position member disposed upon the die and/or die-attach pad, and a molding material encapsulating the leadframe, the die, and the position member together to form the semiconductor package. The method for manufacturing a very thin semiconductor package includes disposing a first position member on one side of the die-attach pad of a leadframe, attaching a die onto the opposite side of the die-attach pad, optionally disposing a second position member on top of the die, electrically connecting the die to the lead terminals of the leadframe, and encapsulating the leadframe, the die, and the position member(s) together to form the very thin semiconductor package.

摘要翻译： 本公开提供了一种非常薄的半导体封装，其包括具有管芯附接焊盘和多个引线端子的引线框架，附接到管芯附接焊盘并且通过接合线电连接到引线端子的管芯，位置构件设置在 模具和/或管芯附接垫，以及将引线框，模具和位置构件封装在一起以形成半导体封装的成型材料。 用于制造非常薄的半导体封装的方法包括在引线框的管芯安装焊盘的一侧上设置第一位置构件，将管芯附接到管芯附接衬垫的相对侧上，可选地将第二位置构件设置在顶部 的模具，将管芯电连接到引线框架的引线端子，并将引线框架，模具和位置构件封装在一起以形成非常薄的半导体封装。