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    Memory module and memory system comprising memory module
    11.
    发明授权
    Memory module and memory system comprising memory module 有权
    内存模块和内存系统，包括内存模块

    公开(公告)号：US08547761B2

    公开(公告)日：2013-10-01

    申请号：US12897189

    申请日：2010-10-04

    Applicant: Seok-Il Kim ,  You-Keun Han ,  Jung-Joon Lee

    Inventor： Seok-Il Kim ,  You-Keun Han ,  Jung-Joon Lee

    IPC: G11C7/00

    CPC classification number: G06F13/16 ,  G06F13/4086 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A memory module comprises a plurality of semiconductor memory devices each having a termination circuit for a command/address bus. The semiconductor memory devices are formed in a substrate of the memory module, and they operate in response to a command/address signal, a data signal, and a termination resistance control signal.

    Abstract translation: 存储器模块包括多个半导体存储器件，每个半导体存储器件具有用于命令/地址总线的终端电路。 半导体存储器件形成在存储器模块的衬底中，并且它们响应于命令/地址信号，数据信号和终端电阻控制信号而工作。

    DATA RECEIVER, SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING THE SAME
    13.
    发明申请
    DATA RECEIVER, SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING THE SAME 有权
    数据接收器，半导体器件和包括其的存储器件

    公开(公告)号：US20120014156A1

    公开(公告)日：2012-01-19

    申请号：US13110161

    申请日：2011-05-18

    Applicant: Sung-Joo PARK ,  Jea-Eun Lee ,  Jung-Joon Lee ,  Yang-Ki Kim ,  Kyoung-Sun Kim

    Inventor： Sung-Joo PARK ,  Jea-Eun Lee ,  Jung-Joon Lee ,  Yang-Ki Kim ,  Kyoung-Sun Kim

    IPC: G11C5/02 ,  G11C7/10 ,  H03L5/00

    CPC classification number: G11C7/1078 ,  G11C7/1084 ,  G11C8/06

    Abstract: A data receiver includes a first buffer circuit and a second buffer circuit. The first buffer circuit varies a resistance of a data path and a resistance of a reference voltage path based on a plurality of control signals, and adjusts a voltage level of an input data signal and a level of a reference voltage to generate an internal data signal and an internal reference voltage based on the varied resistance of the data path and the varied resistance of the reference voltage path. The second buffer circuit compares the internal data signal with the internal reference voltage to generate a data signal.

    Abstract translation: 数据接收机包括第一缓冲电路和第二缓冲电路。 第一缓冲电路基于多个控制信号改变数据路径的电阻和参考电压路径的电阻，并且调整输入数据信号的电压电平和参考电压的电平以产生内部数据信号 以及基于数据路径的变化的电阻和参考电压路径的变化的电阻的内部参考电压。 第二缓冲电路将内部数据信号与内部参考电压进行比较以产生数据信号。

    Semiconductor memory device and memory system using same
    14.
    发明授权
    Semiconductor memory device and memory system using same 失效
    半导体存储器件和使用其的存储器系统

    公开(公告)号：US07663944B2

    公开(公告)日：2010-02-16

    申请号：US11352009

    申请日：2006-02-11

    Applicant: Jung-Joon Lee

    Inventor： Jung-Joon Lee

    IPC: G11C29/00

    CPC classification number: G11C7/20 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254

    Abstract: A semiconductor memory device includes an input data delay time adjustor for varying an input delay time, selecting one bit of a n-bit input data, delaying the selected one bit by the input delay time and outputting the delayed bit, in response to a control signal during an input data delay test operation; and an output data delay time adjustor for varying an output delay time, selecting one bit of a m-bit output data, delaying the selected one bit by the output delay time and outputting the delayed bit, in response to the control signal during an output data delay test operation, wherein the input data delay time adjustor is arranged for n-bit input data, and wherein the output data delay time adjustor is arranged for m-bit output data.

    Abstract translation: 半导体存储器件包括用于改变输入延迟时间的输入数据延迟时间调整器，选择n位输入数据的一位，响应于控制将所选择的一位延迟输入延迟时间并输出延迟位 在输入数据延迟测试操作期间信号; 以及输出数据延迟时间调整器，用于改变输出延迟时间，选择m位输出数据的一位，响应于输出期间的控制信号，将所选择的一位延迟输出延迟时间并输出延迟位 数据延迟测试操作，其中输入数据延迟时间调节器被配置用于n位输入数据，并且其中输出数据延迟时间调整器被布置用于m位输出数据。

    Geldanamycin Derivatives and the Method for Biosynthesis Thereof
    16.
    发明申请
    Geldanamycin Derivatives and the Method for Biosynthesis Thereof 审中-公开
    格尔德霉素衍生物及其生物合成方法

    公开(公告)号：US20080275039A1

    公开(公告)日：2008-11-06

    申请号：US11573503

    申请日：2005-08-11

    Applicant: Jung Joon Lee ,  Young Soo Hong ,  Dongho Lee ,  Jeong-Hyung Lee ,  Kwang-Soo Sung

    Inventor： Jung Joon Lee ,  Young Soo Hong ,  Dongho Lee ,  Jeong-Hyung Lee ,  Kwang-Soo Sung

    IPC: A61K31/5377 ,  C07D225/06 ,  C07H21/04 ,  C12N1/20 ,  C12P17/10 ,  C12N15/64 ,  A61P31/04 ,  A61P37/06 ,  A61P35/00 ,  A61P31/12 ,  A61P31/10

    CPC classification number: C07D225/06

    Abstract: The present invention relates to geldanamycin derivatives, benzoquinone ansamycin biosynthesized by gene manipulation of Streptomyces hygroscopicus subsp. duamyceticus and the method producing them, more particularly to a geldanamycin O-carbamoyl transferase gene(gel8)-inactive mutant, the method producing it and geldanamycin derivatives, 4,5-dihydro-7-O-descarbamoyl-7-hydroxy geldanamycin and 4,5-dihydro-7-O-descarbamoyl-7-hydroxy-17-O-demethyl geldanamycin. Since geldanamycin derivatives of the present invention suppress Hsp90 like geldanamycin, they can effectively be used for antibiotic, antifungal, antiviral, anti-inflammatory and antitumor agents and an immune suppressant.

    Abstract translation: 本发明涉及通过吸湿链霉菌subsp。的基因操作生物合成的格尔德霉素衍生物，苯醌安莎霉素。 杜马霉素及其制备方法，更具体地涉及格尔德霉素O-氨基甲酰基转移酶基因（gel8） - 活性突变体，其制备方法和格尔德霉素衍生物，4,5-二氢-7-O-氨基甲酰基-7-羟基格尔德霉素和4 ，5-二氢-7-O-氨基甲酰基-7-羟基-17-O-脱甲基格尔德霉素。 由于本发明的格尔德霉素衍生物抑制类似格尔德霉素的Hsp90，因此它们可以有效地用于抗生素，抗真菌剂，抗病毒剂，抗炎剂和抗肿瘤剂和免疫抑制剂。

    Method of mounting memory device on PCB for memory module
    17.
    发明授权
    Method of mounting memory device on PCB for memory module 有权
    将存储器件安装在PCB上用于存储器模块的方法

    公开(公告)号：US07348219B2

    公开(公告)日：2008-03-25

    申请号：US11301142

    申请日：2005-12-12

    Applicant: Do-Hyung Kim ,  Chang-Woo Koo ,  Jung-Joon Lee ,  Ki-Hyun Ko

    Inventor： Do-Hyung Kim ,  Chang-Woo Koo ,  Jung-Joon Lee ,  Ki-Hyun Ko

    IPC: H01L21/50 ,  H05K7/00

    CPC classification number: G11C5/04 ,  H05K1/181 ,  H05K2201/09418 ,  H05K2201/10159 ,  H05K2203/1572 ,  Y02P70/611

    Abstract: A memory module and a method of mounting memory devices on a PCB to form the memory module substantially reduce unnecessary routing space and improve signal attenuation characteristics. In the method of mounting and sequentially connecting at least two memory devices on a printed circuit board (PCB) having an axis of elongation to form a memory module, at least one of the memory devices is mounted on at least one face of the PCB so that a base line along an longitudinal axis of the at least one memory device lies at an acute angle with respect to the axis of elongation of the PCB.

    Abstract translation: 存储器模块和将存储器件安装在PCB上以形成存储器模块的方法基本上减少不必要的路由空间并改善信号衰减特性。 在将具有延伸轴的印刷电路板（PCB）上的至少两个存储器件安装并顺序地连接以形成存储器模块的方法中，至少一个存储器件安装在PCB的至少一个面上， 沿着至少一个存储器装置的纵向轴线的基线相对于PCB的伸长轴线成锐角。

    Memory module and a method of arranging a signal line of the same
    18.
    发明申请
    Memory module and a method of arranging a signal line of the same 失效
    存储器模块及其配置信号线的方法

    公开(公告)号：US20050185439A1

    公开(公告)日：2005-08-25

    申请号：US11064671

    申请日：2005-02-24

    Applicant: Chil-Nam Yoon ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Young-Jun Park ,  Il-Sung Yu

    Inventor： Chil-Nam Yoon ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Young-Jun Park ,  Il-Sung Yu

    IPC: G06F12/00 ,  G11C5/06 ,  G11C11/401 ,  H05K1/18

    CPC classification number: G11C5/063 ,  H05K1/181 ,  H05K2201/09254 ,  Y02P70/611

    Abstract: The present invention discloses a memory module and a method of arranging a signal line of the same. The method of arranging a signal line of a memory module comprises: classifying a plurality of memories into a first group including an odd number of memories and a second group including an even number of memories; arranging first branch points corresponding to the plurality of memories and respectively connecting the first branch points to the plurality of memories through first signal lines; arranging a second branch point located at a middle of the second group for respectively connecting between the first branch points adjacent to each other of the second group and between the first branch points adjacent to the second branch points and the second branch point through second signal lines; arranging a third branch point located at a middle of the second group, receiving an external signal, and connecting the third branch point and the second branch point of the second group through a third signal line; and connecting between the second branch point of the second group and the first branch point of the first group through a fourth signal line.

    Abstract translation: 本发明公开了一种存储模块及其配置信号线的方法。 布置存储器模块的信号线的方法包括：将多个存储器分类为包括奇数个存储器的第一组和包括偶数个存储器的第二组; 布置与多个存储器相对应的第一分支点，并通过第一信号线分别将第一分支点连接到多个存储器; 布置位于第二组中间的第二分支点，以分别连接第二组彼此相邻的第一分支点与第二分支点相邻的第一分支点与第二分支点之间通过第二信号线 ; 布置位于第二组中间的第三分支点，接收外部信号，并通过第三信号线连接第二组的第三分支点和第二分支点; 并且通过第四信号线连接第二组的第二分支点和第一组的第一分支点。

    Module having test architecture for facilitating the testing of ball grid array packages, and test method using the same
    20.
    发明授权
    Module having test architecture for facilitating the testing of ball grid array packages, and test method using the same 失效
    具有用于促进球栅阵列封装测试的测试架构的模块，以及使用其的测试方法

    公开(公告)号：US06836138B1

    公开(公告)日：2004-12-28

    申请号：US10795507

    申请日：2004-03-09

    Applicant: Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee

    Inventor： Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee

    IPC: G01R3126

    CPC classification number: H05K1/0268 ,  G01R1/0483 ,  G01R31/31905 ,  G11C29/48 ,  G11C2029/5602 ,  H01L2224/48091 ,  H01L2224/859 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/111 ,  H05K2201/10734 ,  H01L2924/00014

    Abstract: A ball grid array (BGA) package test module includes BGA packages, a module board, and test architecture for use in testing the BGA packages while they are mounted to the module board. The test architecture of the BGA package test module includes package test signal lines connected to solder balls of the BGA packages as extending along a bottom surface of the BGA packages, board test signal lines extending along the module board, and electrical junctions that interconnect the package and board test signal lines. Signals from the BGA packages can be picked up by the probe of a testing apparatus via the board test signal lines. The present invention is advantageous in that it minimizes the effect of stubbing by the test signal lines when the memory module is operating.

    Abstract translation: 球栅阵列（BGA）封装测试模块包括BGA封装，模块板和测试架构，用于在安装到模块板时测试BGA封装。 BGA封装测试模块的测试架构包括连接到BGA封装的焊球的封装测试信号线，沿BGA封装的底表面延伸，沿着模块板延伸的板测试信号线，以及将封装相互连接的电连接 和板测试信号线。 来自BGA封装的信号可以由测试装置的探头通过板测试信号线拾取。 本发明的优点在于，当存储器模块运行时，其最小化由测试信号线引起的短截线的影响。

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