Abstract:
A chemical mechanical polishing machine and a fabrication process using the same. The chemical mechanical polishing machine comprises a retainer ring having a plurality of slurry passages at the bottom of the retainer ring. The retainer ring further comprises a circular path. By conducting the slurry through the slurry passages and the circular, a wafer is planarized within the chemical mechanical polishing machine.
Abstract:
A method for effectively cleaning the slurry remnants left on a polishing pad after the completion of a chemical mechanical polish (CMP) process is provided. This method is able to substantially thoroughly clean away all of the slurry remnants left on the polishing pad. In the method of the invention, the first step is to prepare a cleaning agent which is a mixture of H.sub.2 O.sub.2, deionized water, an acid solution, and an alkaline solution mixed to a predetermined ratio. The cleaning agent is subsequently directed to a nozzle formed in the pad dresser. This allows the cleaning agent to be jetted forcibly onto the slurry remnants on the polishing pad so as to clean the slurry remnants away from the polishing pad. The cleaning agent can be provided with predetermined ratios for various kinds of slurries so that the cleaning agent can be adjusted to be either acid or alkaline in nature. This can allow an increase in the repellent force between the particles of the slurry remnants and the underlying polishing pad that is caused by the so-called zeta potential, thus allowing the slurry remnants to be more easily removed from the polishing pad.
Abstract:
A femtocell and a resource control method thereof are provided. The femtocell comprises a processor and a transceiver. The processor is configured to determine that a service resource of the femtocell reaches a saturation value, reduce a transmitting power of a primary common pilot channel power signal, and set a parameter of a system information block message as a barred state. The transceiver is electrically connected to the processor and configured to transmit the primary common pilot channel power signal and the system information block message.
Abstract:
A chemical-mechanical polishing process for forming a conductive interconnect includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a cap layer is formed over the polished dielectric layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH.sub.4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH.sub.2Cl.sub.2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second conductive line that couples electrically with the first conductive line through the via opening.
Abstract:
A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 Angstroms can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.
Abstract:
A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 Angstroms can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.
Abstract:
A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 Å can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.
Abstract:
The present invention provides a method of preventing the dishing phenomenon occurring atop a dual damascene structure on a semiconductor wafer. The semiconductor has a substrate, a first dielectric layer positioned on the substrate, a dual damascene hole positioned in the first dielectric layer through to the surface of the substrate, a barrier layer covering the surface of the first dielectric layer and both the surface of the walls and bottom of the dual damascene hole, and a copper layer positioned on the barrier layer and filling the dual damascene hole to form the dual damascene structure. The method first involves performing a first chemical mechanical polishing (CMP) process to remove portions of the copper layer down to the surface of the barrier layer. A photoresist layer is then formed atop the dual damascene structure to remove portions of the barrier layer uncovered by the photoresist layer. Finally, a second CMP process is performed to remove portions of the copper layer so as to align the top of the copper layer in the dual damascene structure with the surface of the first dielectric layer after the photoresist layer is stripped.
Abstract:
A semiconductor wafer includes a substrate, an aluminum layer on the substrate, an anti-reflection coating on the aluminum layer, a dielectric layer on the anti-reflection coating, and a via hole that passes through the dielectric layer and the anti-reflection coating down to a predetermined depth within the aluminum layer. A titanium layer is formed on the bottom and on the walls of the via hole. A physical vapor deposition process is then performed to form a first titanium nitride layer on the titanium layer. A chemical vapor deposition process is then performed to form a second titanium nitride layer on the first titanium nitride layer.
Abstract:
A chemical mechanical polishing machine and a fabrication process using the same. The chemical mechanical polishing machine comprises a retainer ring having a plurality of slurry passages at the bottom of the retainer ring. The retainer ring further comprises a circular path. By conducting the slurry through the slurry passages and the circular, a wafer is planarized within the chemical mechanical polishing machine.