Method of cleaning slurry remnants after the completion of a
chemical-mechanical polish process
    12.
    发明授权
    Method of cleaning slurry remnants after the completion of a chemical-mechanical polish process 失效
    在化学机械抛光工艺完成后清洗浆料残留物的方法

    公开(公告)号:US5876508A

    公开(公告)日:1999-03-02

    申请号:US818898

    申请日:1997-03-17

    Abstract: A method for effectively cleaning the slurry remnants left on a polishing pad after the completion of a chemical mechanical polish (CMP) process is provided. This method is able to substantially thoroughly clean away all of the slurry remnants left on the polishing pad. In the method of the invention, the first step is to prepare a cleaning agent which is a mixture of H.sub.2 O.sub.2, deionized water, an acid solution, and an alkaline solution mixed to a predetermined ratio. The cleaning agent is subsequently directed to a nozzle formed in the pad dresser. This allows the cleaning agent to be jetted forcibly onto the slurry remnants on the polishing pad so as to clean the slurry remnants away from the polishing pad. The cleaning agent can be provided with predetermined ratios for various kinds of slurries so that the cleaning agent can be adjusted to be either acid or alkaline in nature. This can allow an increase in the repellent force between the particles of the slurry remnants and the underlying polishing pad that is caused by the so-called zeta potential, thus allowing the slurry remnants to be more easily removed from the polishing pad.

    Abstract translation: 提供了在完成化学机械抛光(CMP)工艺之后有效地清洁留在抛光垫上的浆料残余物的方法。 该方法能够基本上彻底地清除留在抛光垫上的所有浆料残余物。 在本发明的方法中,第一步是制备一种清洗剂,它是以预定比例混合的H 2 O 2,去离子水,酸性溶液和碱性溶液的混合物。 随后将清洁剂引导到形成在修整器中的喷嘴。 这样可以将洗涤剂强制地喷射到抛光垫上的浆料残余物上,以清除离开抛光垫的浆料残余物。 可以为各种浆料提供预定比例的清洗剂,使清洗剂本质上可以调节为酸性或碱性。 这可以增加由所谓的ζ电位引起的浆料残留物的颗粒和下面的抛光垫之间的驱除力,从而使浆料残余物更容易从抛光垫上去除。

    FEMTOCELL AND RESOURCE CONTROL METHOD THEREOF
    13.
    发明申请
    FEMTOCELL AND RESOURCE CONTROL METHOD THEREOF 审中-公开
    FEMTOCELL和资源控制方法

    公开(公告)号:US20130107866A1

    公开(公告)日:2013-05-02

    申请号:US13312226

    申请日:2011-12-06

    Abstract: A femtocell and a resource control method thereof are provided. The femtocell comprises a processor and a transceiver. The processor is configured to determine that a service resource of the femtocell reaches a saturation value, reduce a transmitting power of a primary common pilot channel power signal, and set a parameter of a system information block message as a barred state. The transceiver is electrically connected to the processor and configured to transmit the primary common pilot channel power signal and the system information block message.

    Abstract translation: 提供了一种毫微微小区及其资源控制方法。 毫微微小区包括处理器和收发器。 处理器被配置为确定毫微微小区的服务资源达到饱和值,降低主公共导频信道功率信号的发送功率,并将系统信息块消息的参数设置为禁止状态。 收发器电连接到处理器并且被配置为发送主公共导频信道功率信号和系统信息块消息。

    CHEMICAL-MECHANICAL POLISHING METHOD
    14.
    发明申请
    CHEMICAL-MECHANICAL POLISHING METHOD 有权
    化学机械抛光方法

    公开(公告)号:US20080102635A1

    公开(公告)日:2008-05-01

    申请号:US11965757

    申请日:2007-12-28

    Abstract: A chemical-mechanical polishing process for forming a conductive interconnect includes the steps of providing a semiconductor substrate having a first conductive line thereon, and then forming at least one dielectric layer over the substrate and the first conductive line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a cap layer is formed over the polished dielectric layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH.sub.4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH.sub.2Cl.sub.2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second conductive line that couples electrically with the first conductive line through the via opening.

    Abstract translation: 用于形成导电互连的化学机械抛光工艺包括以下步骤:提供其上具有第一导电线的半导体衬底,然后在衬底和第一导电线上形成至少一个电介质层。 接下来,使用化学 - 机械抛光方法来抛光电介质层的表面。 此后,在抛光的介电层上形成覆盖层。 形成盖层的方法包括使用硅烷(SiH 4)或四乙基原硅酸盐(TEOS)作为主要反应剂的化学气相沉积法沉积氧化硅。 或者,可以通过使用化学气相沉积法以硅烷或二氯硅氢化钠(SiH 2 Cl 2)作为主要反应剂沉积氮化硅来形成覆盖层。 最后,通过介电层和盖层形成通孔,以及通过通路孔与第一导电线电连接的第二导线。

    Chemical-mechanical polishing method
    15.
    发明授权
    Chemical-mechanical polishing method 有权
    化学机械抛光方法

    公开(公告)号:US07335598B2

    公开(公告)日:2008-02-26

    申请号:US11109896

    申请日:2005-04-19

    Abstract: A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 Angstroms can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.

    Abstract translation: 用于形成金属互连的化学机械抛光工艺包括以下步骤:提供其上具有第一金属线的半导体衬底,然后在衬底和第一金属线上形成电介质层。 接下来,使用化学 - 机械抛光方法来抛光电介质层的表面。 此后,在抛光的介电层上形成薄盖层。 具有1000-3000埃厚度的薄盖层可以是例如二氧化硅层,磷硅酸盐玻璃层或富硅氧化物层。 形成覆盖层的方法包括使用硅烷(SiH 4 S 4)或四乙基原硅酸盐(TEOS)作为主要反应剂的化学气相沉积法沉积氧化硅。 或者,可以通过使用化学气相沉积法以硅烷或二氯硅氢化钠(SiH 2 Cl 2 Cl 2)作为主要反应剂沉积氮化硅来形成覆盖层。 最后,形成通过介电层和盖层的通路开口,并且形成通过通路孔与第一金属线电连接的第二金属线。

    Chemical-mechanical polishing method
    16.
    发明申请
    Chemical-mechanical polishing method 有权
    化学机械抛光方法

    公开(公告)号:US20050186799A1

    公开(公告)日:2005-08-25

    申请号:US11109896

    申请日:2005-04-19

    Abstract: A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 Angstroms can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.

    Abstract translation: 用于形成金属互连的化学机械抛光工艺包括以下步骤:提供其上具有第一金属线的半导体衬底,然后在衬底和第一金属线上形成电介质层。 接下来,使用化学 - 机械抛光方法来抛光电介质层的表面。 此后,在抛光的介电层上形成薄盖层。 具有1000-3000埃厚度的薄盖层可以是例如二氧化硅层,磷硅酸盐玻璃层或富硅氧化物层。 形成覆盖层的方法包括使用硅烷(SiH 4 S 4)或四乙基原硅酸盐(TEOS)作为主要反应剂的化学气相沉积法沉积氧化硅。 或者,可以通过使用化学气相沉积法以硅烷或二氯硅氢化钠(SiH 2 Cl 2 Cl 2)作为主要反应剂沉积氮化硅来形成覆盖层。 最后,形成通过介电层和盖层的通路开口,并且形成通过通路孔与第一金属线电连接的第二金属线。

    Chemical-mechanical polishing method
    17.
    发明授权
    Chemical-mechanical polishing method 有权
    化学机械抛光方法

    公开(公告)号:US06913993B2

    公开(公告)日:2005-07-05

    申请号:US09990948

    申请日:2001-11-20

    Abstract: A chemical-mechanical polishing process for forming a metallic interconnect includes the steps of providing a semiconductor substrate having a first metallic line thereon, and then forming a dielectric layer over the substrate and the first metallic line. Next, a chemical-mechanical polishing method is used to polish the surface of the dielectric layer. Thereafter, a thin cap layer is formed over the polished dielectric layer. The thin cap layer having a thickness of between 1000-3000 Å can be, for example, a silicon dioxide layer, a phosphosilicate glass layer or a silicon-rich oxide layer. The method of forming the cap layer includes depositing silicon oxide using a chemical vapor deposition method with silicane (SiH4) or tetra-ethyl-ortho-silicate (TEOS) as the main reactive agent. Alternatively, the cap layer can be formed by depositing silicon nitride using a chemical vapor deposition method with silicane or silicon dichlorohydride (SiH2Cl2) as the main reactive agent. Finally, a via opening is formed through the dielectric layer and the cap layer, and a second metallic line that couples electrically with the first metallic line through the via opening is formed.

    Abstract translation: 用于形成金属互连的化学机械抛光工艺包括以下步骤:提供其上具有第一金属线的半导体衬底,然后在衬底和第一金属线上形成电介质层。 接下来,使用化学 - 机械抛光方法来抛光电介质层的表面。 此后,在抛光的介电层上形成薄盖层。 厚度在1000-3000之间的薄盖层可以是例如二氧化硅层,磷硅酸盐玻璃层或富硅氧化物层。 形成覆盖层的方法包括使用硅烷(SiH 4 S 4)或四乙基原硅酸盐(TEOS)作为主要反应剂的化学气相沉积法沉积氧化硅。 或者,可以通过使用化学气相沉积法以硅烷或二氯硅氢化钠(SiH 2 Cl 2 Cl 2)作为主要反应剂沉积氮化硅来形成覆盖层。 最后,形成通过介电层和盖层的通路开口,并且形成通过通路孔与第一金属线电连接的第二金属线。

    Method of preventing dishing phenomenon atop a dual damascene structure
    18.
    发明授权
    Method of preventing dishing phenomenon atop a dual damascene structure 失效
    防止双镶嵌结构顶部凹陷现象的方法

    公开(公告)号:US06399503B1

    公开(公告)日:2002-06-04

    申请号:US09764329

    申请日:2001-01-19

    CPC classification number: H01L21/7684 H01L21/3212

    Abstract: The present invention provides a method of preventing the dishing phenomenon occurring atop a dual damascene structure on a semiconductor wafer. The semiconductor has a substrate, a first dielectric layer positioned on the substrate, a dual damascene hole positioned in the first dielectric layer through to the surface of the substrate, a barrier layer covering the surface of the first dielectric layer and both the surface of the walls and bottom of the dual damascene hole, and a copper layer positioned on the barrier layer and filling the dual damascene hole to form the dual damascene structure. The method first involves performing a first chemical mechanical polishing (CMP) process to remove portions of the copper layer down to the surface of the barrier layer. A photoresist layer is then formed atop the dual damascene structure to remove portions of the barrier layer uncovered by the photoresist layer. Finally, a second CMP process is performed to remove portions of the copper layer so as to align the top of the copper layer in the dual damascene structure with the surface of the first dielectric layer after the photoresist layer is stripped.

    Abstract translation: 本发明提供一种防止半导体晶片上的双镶嵌结构顶部发生凹陷现象的方法。 半导体具有衬底,位于衬底上的第一电介质层,位于第一电介质层中的双镶嵌孔,穿过衬底的表面,覆盖第一电介质层的表面的阻挡层和 双层镶嵌孔的壁和底部,以及位于阻挡层上的铜层,并填充双镶嵌孔以形成双镶嵌结构。 该方法首先包括进行第一化学机械抛光(CMP)工艺以将铜层的部分去除到阻挡层的表面。 然后在双镶嵌结构顶部形成光致抗蚀剂层以去除未被光致抗蚀剂层覆盖的阻挡层的部分。 最后,执行第二CMP工艺以去除部分铜层,以便在剥离光致抗蚀剂层之后,将双镶嵌结构中的铜层的顶部与第一介电层的表面对准。

    Method for preventing aluminum intrusions
    19.
    发明授权
    Method for preventing aluminum intrusions 失效
    防止铝侵入的方法

    公开(公告)号:US06333261B1

    公开(公告)日:2001-12-25

    申请号:US09584697

    申请日:2000-06-01

    CPC classification number: H01L21/76843

    Abstract: A semiconductor wafer includes a substrate, an aluminum layer on the substrate, an anti-reflection coating on the aluminum layer, a dielectric layer on the anti-reflection coating, and a via hole that passes through the dielectric layer and the anti-reflection coating down to a predetermined depth within the aluminum layer. A titanium layer is formed on the bottom and on the walls of the via hole. A physical vapor deposition process is then performed to form a first titanium nitride layer on the titanium layer. A chemical vapor deposition process is then performed to form a second titanium nitride layer on the first titanium nitride layer.

    Abstract translation: 半导体晶片包括基板,基板上的铝层,铝层上的防反射涂层,防反射涂层上的介电层,以及穿过介电层和防反射涂层的通孔 下降到铝层内的预定深度。 在通孔的底部和壁上形成钛层。 然后进行物理气相沉积工艺以在钛层上形成第一氮化钛层。 然后进行化学气相沉积工艺以在第一氮化钛层上形成第二氮化钛层。

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