公开(公告)号：US07888857B2

公开(公告)日：2011-02-15

申请号：US11534710

申请日：2006-09-25

Applicant: Jae Young Choi ,  Byoung Lyong Choi ,  Dong Kee Yi ,  Kwang Soo Seol ,  Seong Jae Choi

Inventor： Jae Young Choi ,  Byoung Lyong Choi ,  Dong Kee Yi ,  Kwang Soo Seol ,  Seong Jae Choi

IPC: H01J63/04 ,  H01J1/62

CPC classification number: H01L29/06 ,  B82Y20/00 ,  B82Y30/00 ,  H01L51/502 ,  H01L51/52

Abstract: A three-dimensional light emitting device and a method for fabricating the light emitting device are provided. The light emitting device comprises a substrate and a semiconductor nanoparticle layer wherein the substrate is provided with a plurality of three-dimensional recesses and the surface having the recesses is coated with semiconductor nanoparticles. According to the three-dimensional light emitting device, the formation of the semiconductor nanoparticles on the surface of the recessed substrate increases the light emitting area and enhances the luminescence intensity, leading to an increase in the amount of light emitted from the light emitting device per unit area. Therefore, the three-dimensional light emitting device has the advantage of improved luminescence efficiency.

Abstract translation: 提供三维发光器件和制造发光器件的方法。 发光器件包括衬底和半导体纳米颗粒层，其中衬底设置有多个三维凹槽，并且具有凹陷的表面涂覆有半导体纳米颗粒。 根据三维发光装置，在凹陷基板的表面上形成半导体纳米颗粒增加发光面积并增强发光强度，导致从发光装置发射的光量增加 单位面积 因此，三维发光装置具有提高发光效率的优点。

公开(公告)号：US07838422B2

公开(公告)日：2010-11-23

申请号：US11892849

申请日：2007-08-28

Applicant: Eun-ha Lee ,  Hion-suck Baik ,  Kwang-soo Seol ,  Sang-jin Park ,  Jong-bong Park ,  Min-ho Yang

Inventor： Eun-ha Lee ,  Hion-suck Baik ,  Kwang-soo Seol ,  Sang-jin Park ,  Jong-bong Park ,  Min-ho Yang

IPC: H01L21/44

CPC classification number: H01L29/42332 ,  Y10T428/259

Abstract: Provided is an aluminum (Al) doped charge trap layer, a non-volatile memory device and methods of fabricating the same. The charge trap layer may include a plurality of silicon nano dots that trap charges and a silicon oxide layer that covers the silicon nano dots, wherein the charge trap layer is doped with aluminum (Al). The non-volatile memory device may include a substrate including a source and a drain on separate regions of the substrate, a tunneling film on the substrate contacting the source and the drain, the charge trap layer according to example embodiments, a blocking film on the charge trap layer, and a gate electrode on the blocking film.

Abstract translation: 提供了铝（Al）掺杂的电荷阱层，非易失性存储器件及其制造方法。 电荷陷阱层可以包括捕获电荷的多个硅纳米点和覆盖硅纳米点的氧化硅层，其中电荷陷阱层掺杂有铝（Al）。 非挥发性存储器件可以包括衬底，该衬底包括在衬底的分离区域上的源极和漏极，在衬底上接触源极和漏极的隧道膜，根据示例性实施例的电荷陷阱层， 电荷陷阱层和阻挡膜上的栅电极。

公开(公告)号：US07795159B2

公开(公告)日：2010-09-14

申请号：US11987425

申请日：2007-11-30

Applicant: Kwang-soo Seol ,  Yo-sep Min ,  Sang-min Shin

Inventor： Kwang-soo Seol ,  Yo-sep Min ,  Sang-min Shin

IPC: H01L21/31

CPC classification number: H01L29/792 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7883 ,  Y10T428/31678

Abstract: Provided are a charge trap semiconductor memory device including a charge trap layer on a semiconductor substrate, and a method of manufacturing the charge trap semiconductor memory device. The method includes: (a) coating a first precursor material on a surface of a semiconductor substrate to be deposited and oxidizing the first precursor material to form a first layer formed of an insulating material; (b) coating a second precursor material formed of metallicity on the first layer; (c) supplying the first precursor material on the surface coated with the second precursor material to substitute the second precursor material with the first precursor material; and (d) oxidizing the first and second precursor materials obtained in (c) to form a second layer formed of an insulating material and a metal impurity, and (a) through (d) are performed at least one time to form a charge trap layer having a structure in which the metal impurity is isolated in the insulating material.

Abstract translation: 提供了一种在半导体衬底上包括电荷陷阱层的电荷陷阱半导体存储器件，以及制造电荷阱半导体存储器件的方法。 该方法包括：（a）在待沉积的半导体衬底的表面上涂覆第一前体材料并氧化第一前体材料以形成由绝缘材料形成的第一层; （b）在第一层上涂覆由金属性形成的第二前体材料; （c）在涂覆有第二前体材料的表面上提供第一前体材料以用第一前体材料代替第二前体材料; 和（d）氧化由（c）中得到的第一和第二前体材料以形成由绝缘材料和金属杂质形成的第二层，并且（a）至（d）至少进行一次以形成电荷阱 具有金属杂质在绝缘材料中隔离的结构的层。

公开(公告)号：US07760551B2

公开(公告)日：2010-07-20

申请号：US12232082

申请日：2008-09-10

Applicant: Sang-jin Park ,  Kwang-soo Seol ,  Ki-hwan Choi ,  Jung-hun Sung ,  Sang-moo Choi

Inventor： Sang-jin Park ,  Kwang-soo Seol ,  Ki-hwan Choi ,  Jung-hun Sung ,  Sang-moo Choi

IPC: G11C16/04

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3413 ,  G11C16/3454 ,  G11C16/3486

Abstract: A method of programming a nonvolatile memory device may include applying a program voltage to a memory cell. A supplementary pulse may be applied to the memory cell to facilitate thermalization of charges after the application of the program voltage. A recovery voltage may be applied to the memory cell after the application of the supplementary pulse. A program state of the memory cell may be verified using a verification voltage after the application of the recovery voltage.

Abstract translation: 非易失性存储器件的编程方法可以包括将程序电压施加到存储单元。 补充脉冲可以施加到存储器单元，以便在施加编程电压之后促进电荷的热化。 在施加补充脉冲之后，可以将复原电压施加到存储单元。 可以在施加恢复电压之后使用验证电压来验证存储器单元的编程状态。

公开(公告)号：US07675786B2

公开(公告)日：2010-03-09

申请号：US11898709

申请日：2007-09-14

Applicant: Sang-jin Park ,  In-jun Hwang ,  Jae-woong Hyun ,  Yoon-dong Park ,  Kwang-soo Seol ,  Sang-min Shin ,  Sang-moo Choi ,  Ju-hee Park

Inventor： Sang-jin Park ,  In-jun Hwang ,  Jae-woong Hyun ,  Yoon-dong Park ,  Kwang-soo Seol ,  Sang-min Shin ,  Sang-moo Choi ,  Ju-hee Park

IPC: G11C16/04

CPC classification number: H01L29/66825 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

Abstract: A semiconductor memory device may include a semiconductor substrate, a control gate electrode recessed in the semiconductor substrate, a storage node layer between the control gate electrode and the semiconductor substrate, a tunneling insulating layer between the storage node layer and the semiconductor substrate, a blocking insulating layer between the storage node layer and the control gate electrode, and first and second channel regions surrounding the control gate electrode and separated by a pair of opposing separating insulating layers. A method of operating the semiconductor memory device may include programming data in the storage node layer by charge tunneling through the blocking insulating layer, thus achieving relatively high reliability and efficiency.

Abstract translation: 半导体存储器件可以包括半导体衬底，凹入半导体衬底中的控制栅电极，控制栅电极和半导体衬底之间的存储节点层，存储节点层和半导体衬底之间的隧穿绝缘层， 存储节点层和控制栅电极之间的绝缘层以及围绕控制栅电极并由一对相对的分隔绝缘层隔开的第一和第二沟道区。 操作半导体存储器件的方法可以包括通过阻塞绝缘层进行电荷隧穿而在存储节点层中编程数据，从而实现相对较高的可靠性和效率。

公开(公告)号：US20100044779A1

公开(公告)日：2010-02-25

申请号：US12461612

申请日：2009-08-18

Applicant: Kwang-Soo Seol

Inventor： Kwang-Soo Seol

IPC: H01L29/792

CPC classification number: H01L29/42344 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/792

Abstract: Memory devices is provided, the memory devices include a tunneling insulating layer disposed on a substrate, a charge storage layer disposed on the tunneling insulating layer, a blocking insulating layer disposed on the charge storage layer and a control gate electrode disposed on the blocking insulating layer. The control gate electrode may have an edge portion spaced farther apart from the blocking insulating layer than a central portion of the control gate electrode to concentrate charge density distribution on a central portion of a memory cell.

Abstract translation: 提供存储器件，存储器件包括设置在衬底上的隧道绝缘层，设置在隧道绝缘层上的电荷存储层，设置在电荷存储层上的阻挡绝缘层和设置在阻挡绝缘层上的控制栅电极 。 与控制栅极的中心部分相比，控制栅电极可以具有与阻挡绝缘层相距更远的边缘部分，以将电荷密度分布集中在存储器单元的中心部分上。

公开(公告)号：US20100008136A1

公开(公告)日：2010-01-14

申请号：US12458294

申请日：2009-07-08

Applicant: Kwang-soo Seol ,  Sung-Il Park ,  Yoon-dong Park ,  Young-gu Jin ,  In-sung Joe

Inventor： Kwang-soo Seol ,  Sung-Il Park ,  Yoon-dong Park ,  Young-gu Jin ,  In-sung Joe

IPC: G11C16/06 ,  G11C16/04

CPC classification number: G11C16/3454 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C2211/5621

Abstract: Provided are methods of operating NAND nonvolatile memory devices. The operating methods include applying a read voltage or a verify voltage to a selected memory cell from among a plurality of memory cells of a cell string to verify or read a programmed state of the selected memory cell; applying a first pass voltage to non-selected memory cells closest to the selected memory cell of the cell string; applying a second pass voltage to second closest non-selected memory cells to the selected memory cell; and applying a third pass voltage to other non-selected memory cells, where the first pass voltage is less than each of the second and third pass voltages and the second pass voltage is greater than the third pass voltage.

Abstract translation: 提供了操作NAND非易失性存储器件的方法。 操作方法包括从单元串的多个存储单元中向所选存储单元施加读取电压或验证电压以验证或读取所选存储单元的编程状态; 对最靠近所述单元串的选定存储单元的未选择存储单元施加第一通过电压; 将第二通过电压施加到所选择的存储器单元的第二最近的未选择的存储器单元; 以及向其他未选择的存储单元施加第三通过电压，其中第一通过电压小于第二和第三通过电压中的每一个，并且第二通过电压大于第三通过电压。

公开(公告)号：US20090117697A1

公开(公告)日：2009-05-07

申请号：US12318097

申请日：2008-12-22

Applicant: Sang-Ji Park ,  Myoung-Jae Lee ,  Young-Kwan Cha ,  Sun-Ae Seo ,  Kyung-Sang Cho ,  Kwang-Soo Seol

Inventor： Sang-Ji Park ,  Myoung-Jae Lee ,  Young-Kwan Cha ,  Sun-Ae Seo ,  Kyung-Sang Cho ,  Kwang-Soo Seol

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L27/101 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/146 ,  H01L45/1608

Abstract: A nonvolatile memory device including a nano dot and a method of fabricating the same are provided. The nonvolatile memory device may include a lower electrode, an oxide layer on the lower electrode, a nano dot in the oxide layer and an upper electrode on the oxide layer. In example embodiments, the current paths inside the oxide layer may be unified, thereby stabilizing the reset current.

Abstract translation: 提供了包括纳米点的非易失性存储器件及其制造方法。 非易失性存储器件可以包括下电极，下电极上的氧化物层，氧化物层中的纳米点和氧化物层上的上电极。 在示例性实施例中，氧化物层内的电流路径可以是统一的，从而稳定复位电流。

公开(公告)号：US20090071934A1

公开(公告)日：2009-03-19

申请号：US12219987

申请日：2008-07-31

Applicant: Sang-moo Choi ,  Jung-hun Sung ,  Kwang-soo Seol ,  Woong-chul Shin ,  Sang-jin Park

Inventor： Sang-moo Choi ,  Jung-hun Sung ,  Kwang-soo Seol ,  Woong-chul Shin ,  Sang-jin Park

IPC: B44C1/22 ,  B05D3/10 ,  C23C14/08 ,  C23C16/00

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518

Abstract: Crystalline aluminum oxide layers having increased energy band gap, charge trap memory devices including crystalline aluminum oxide layers and methods of manufacturing the same are provided. A method of forming an aluminum oxide layer having an increased energy band gap includes forming an amorphous aluminum oxide layer on a lower film, introducing hydrogen (H) or hydroxyl group (OH) into the amorphous aluminum oxide layer, and crystallizing the amorphous aluminum oxide layer including the H or OH.

Abstract translation: 提供具有增加的能带隙的结晶氧化铝层，包括结晶氧化铝层的电荷陷阱存储器件及其制造方法。 形成具有增加的能带隙的氧化铝层的方法包括在下膜上形成无定形氧化铝层，将氢（H）或羟基（OH）引入到无定形氧化铝层中，并使非晶态氧化铝 层包括H或OH。

公开(公告)号：US20090067247A1

公开(公告)日：2009-03-12

申请号：US12232082

申请日：2008-09-10

Applicant: Sang-jin Park ,  Kwang-soo Seol ,  Ki-hwan Choi ,  Jung-hun Sung ,  Sang-moo Choi

Inventor： Sang-jin Park ,  Kwang-soo Seol ,  Ki-hwan Choi ,  Jung-hun Sung ,  Sang-moo Choi

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/3413 ,  G11C16/3454 ,  G11C16/3486

Abstract: A method of programming a nonvolatile memory device may include applying a program voltage to a memory cell. A supplementary pulse may be applied to the memory cell to facilitate thermalization of charges after the application of the program voltage. A recovery voltage may be applied to the memory cell after the application of the supplementary pulse. A program state of the memory cell may be verified using a verification voltage after the application of the recovery voltage.

Abstract translation: 非易失性存储器件的编程方法可以包括将程序电压施加到存储单元。 补充脉冲可以施加到存储器单元，以便在施加编程电压之后促进电荷的热化。 在施加补充脉冲之后，可以将复原电压施加到存储单元。 可以在施加恢复电压之后使用验证电压来验证存储器单元的编程状态。