High purity perfluoroelastomer composites and a process to produce the same
    14.
    发明申请
    High purity perfluoroelastomer composites and a process to produce the same 有权
    高纯度全氟弹性体复合材料及其制备方法

    公开(公告)号:US20090253854A1

    公开(公告)日:2009-10-08

    申请号:US12353514

    申请日:2009-01-14

    Abstract: High purity perfluoroelastomer composites and processes for producing the same are provided. High purity composites may be formed from compositions comprising a crosslinkable fluoroelastomer terpolymer of TFE, PAVE, and CNVE, and functionalized PTFE, which may be crosslinked to form crosslinked composites having low metal content and low compression set. Emulsion mixtures for forming the high purity composites are also provided.

    Abstract translation: 提供了高纯度全氟弹性体复合材料及其制备方法。 高纯度复合材料可以由包含TFE,PAVE和CNVE的交联性含氟弹性体三元共聚物和官能化PTFE的组合物形成,其可以交联以形成具有低金属含量和低压缩永久变形的交联复合材料。 还提供了用于形成高纯度复合材料的乳液混合物。

    Bi-layer capping of low-K dielectric films
    15.
    发明授权
    Bi-layer capping of low-K dielectric films 失效
    低K电介质薄膜的双层封盖

    公开(公告)号:US07598183B2

    公开(公告)日:2009-10-06

    申请号:US11533505

    申请日:2006-09-20

    Abstract: A method is provided for processing a substrate surface by delivering a first gas mixture comprising a first organosilicon compound, a first oxidizing gas, and one or more hydrocarbon compounds into a chamber at deposition conditions sufficient to deposit a first low dielectric constant film on the substrate surface. A second gas mixture having a second organosilicon compound and a second oxidizing gas is delivered into the chamber at deposition conditions sufficient to deposit a second low dielectric constant film on the first low dielectric constant film. The flow rate of the second oxidizing gas into the chamber is increased, and the flow rate of the second organosilicon compound into the chamber is decreased to deposit an oxide rich cap on the second low dielectric constant film.

    Abstract translation: 提供了一种通过将包含第一有机硅化合物,第一氧化气体和一种或多种烃化合物的第一气体混合物输送到室中的方法来处理衬底表面,该沉积条件足以在衬底上沉积第一低介电常数膜 表面。 具有第二有机硅化合物和第二氧化气体的第二气体混合物在足以在第一低介电常数膜上沉积第二低介电常数膜的沉积条件下被输送到室中。 进入室内的第二氧化气体的流量增加,第二有机硅化合物进入室的流量减少,从而在第二低介电常数膜上沉积氧化物富集盖。

    DROUGHT TOLERANCE IN PLANTS
    16.
    发明申请
    DROUGHT TOLERANCE IN PLANTS 审中-公开
    耐旱的植物

    公开(公告)号:US20080052791A1

    公开(公告)日:2008-02-28

    申请号:US11668356

    申请日:2007-01-29

    CPC classification number: C12N15/8273 A01H3/00 A01N63/00 A01N63/02

    Abstract: The invention provides methods for enhancing drought tolerance in a plant, by infecting the plant with a plant virus, or infectious material derived from a plant virus. The plant thereby displays fewer, less severe, and/or delayed symptoms of dehydration. The reduction in symptoms allows for improved plant growth.

    Abstract translation: 本发明提供了通过用植物病毒感染植物或从植物病毒衍生的感染性物质来增强植物耐旱性的方法。 因此,该植物显示较少,较不严重和/或延迟的脱水症状。 症状的减少允许改善植物生长。

    Active ESD shunt with transistor feedback to reduce latch-up susceptibility
    19.
    发明授权
    Active ESD shunt with transistor feedback to reduce latch-up susceptibility 有权
    主动ESD分流与晶体管反馈,以减少闭锁敏感性

    公开(公告)号:US06989979B1

    公开(公告)日:2006-01-24

    申请号:US10605321

    申请日:2003-09-22

    CPC classification number: H01L27/0285

    Abstract: A VDD-to-VSS clamp shunts current from a power node to a ground node within an integrated circuit chip when an electro-static-discharges (ESD) event occurs. A resistor and capacitor in series between power and ground generates a low voltage on a trigger node between the resistor and capacitor when an ESD event occurs. A p-channel transistor with its gate driven by the trigger node turns on, driving a gate node high. The gate node is the gate of an n-channel shunt transistor that shunts ESD current from power to ground. A p-channel feedback transistor terminates the ESD shunt current. The p-channel feedback transistor is connected between power and the trigger node, in parallel with the resistor, and has the gate node as its gate. When a latch up trigger occurs, such as electron injection, voltage drops across an N-well of the resistor is prevented by the parallel p-channel feed-back transistor.

    Abstract translation: 当发生静电放电(ESD)事件时,VDD至VSS钳位将电流从集成电路芯片内的电源节点分流到接地节点。 电源和地之间串联的电阻和电容在ESD事件发生时在电阻和电容之间的触发节点产生低电压。 由触发器节点驱动的栅极的p沟道晶体管导通,驱动栅极节点。 栅极节点是将ESD电流从电源分流到地的n沟道并联晶体管的栅极。 p沟道反馈晶体管终止ESD分流电流。 p沟道反馈晶体管与电阻并联连接在功率与触发节点之间,栅极节点为栅极。 当发生闩锁触发(例如电子注入)时,由并联的p沟道反馈晶体管阻止电阻器的N阱上的电压降。

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