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    ZQ calibration circuit and method for memory interfaces
    11.
    发明授权
    ZQ calibration circuit and method for memory interfaces 有权

    公开(公告)号：US12216596B2

    公开(公告)日：2025-02-04

    申请号：US17941790

    申请日：2022-09-09

    Applicant: SanDisk Technologies LLC

    Inventor： Mohammad Reza Mahmoodi ,  Martin Lueker-Boden

    IPC: G06F13/16

    Abstract: Systems and methods disclosed herein provide for an improved termination leg unit design and method of trimming impedance thereof, which provides for improved impedance matching for process variations, along with variations in temperature and voltage. Example implementation provide for a leg unit circuit design that includes a first circuit compensating for temperature and voltage variations and a second circuit, connected in series with the first circuit, compensating for process variations. Furthermore, disclosed herein is ZQ calibration method that provides for calibrating of the impedance of each of an on-die termination, a pull-up driver, and a pull-down driver using a single calibration circuit.

    Hybrid smart verify for QLC/TLC die
    12.
    发明授权
    Hybrid smart verify for QLC/TLC die 有权

    公开(公告)号：US12205657B2

    公开(公告)日：2025-01-21

    申请号：US17895412

    申请日：2022-08-25

    Applicant: SanDisk Technologies LLC

    Inventor： Xiang Yang ,  Henry Chin ,  Erika Penzo ,  Muhammad Masuduzzaman

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14

    Abstract: Technology is disclosed herein for smart verify in a memory system that has a four bit per cell program mode (or X4 mode) and also a three bit per cell program mode (or X3 mode). The X3 mode uses a three-bit gray code that is based on a four-bit gray code of the X4 mode. The memory system skips verify of states in the X3 mode, while using a considerable portion of the programming logic from the X4 mode. In one X3 mode the memory system skips B-state verify while the number of memory cells having a Vt above an A-state verify voltage is below a threshold. In one X3 mode the memory system determines whether to skip verify for a first set of data states based on a first test and determines whether to skip verify for a second set of data states based on a second test.

    Concurrent write to programmable resistance memory cells in cross-point array
    13.
    发明授权
    Concurrent write to programmable resistance memory cells in cross-point array 有权

    公开(公告)号：US12205638B2

    公开(公告)日：2025-01-21

    申请号：US17939818

    申请日：2022-09-07

    Applicant: SanDisk Technologies LLC

    Inventor： Nathan Franklin ,  Ward Parkinson ,  Michael Grobis ,  James O'Toole

    IPC: G11C11/56 ,  G11C11/16 ,  H01L23/00 ,  H01L25/065 ,  H10B61/00 ,  H10N50/80 ,  H10N50/85

    Abstract: Concurrent access of multiple memory cells in a cross-point memory array is disclosed. In one aspect, a forced current approach is used in which, while a select voltage is applied to a selected bit line, an access current is driven separately through each selected word line to concurrently drive the access current separately through each selected memory cell. Hence, multiple memory cells are concurrently accessed. In some aspects, the memory cells are accessed using a self-referenced read (SRR), which improves read margin. Concurrently accessing more than one memory cell in a cross-point memory array improves bandwidth. Moreover, such concurrent accessing allows the memory system to be constructed with fewer, but larger cross-point arrays, which increases array efficiency. Moreover, concurrent access as disclosed herein is compatible with memory cells such as MRAM which require bipolar operation.

    THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME
    15.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE WITH THROUGH-STACK CONTACT VIA STRUCTURES AND METHOD OF MAKING THE SAME 有权

    公开(公告)号：US20250014990A1

    公开(公告)日：2025-01-09

    申请号：US18800545

    申请日：2024-08-12

    Applicant: Sandisk Technologies LLC

    Inventor： Tomohiro KUBO ,  Koichi MATSUNO

    IPC: H01L23/522 ,  H01L23/532 ,  H10B43/10 ,  H10B43/27

    Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through each layer within the alternating stack, a memory opening fill structure located in the memory opening and including a vertical stack of memory elements a vertical semiconductor channel, and a contact via structure. The contact via structure includes a conductive pillar portion vertically extending at least from a first horizontal plane including a bottommost surface of the alternating stack to a second horizontal plane including a topmost surface of the alternating stack, and an annular conductive fin portion laterally protruding from the conductive pillar portion and contacting one of the electrically conductive layers. A vertical stack of annular insulating plates laterally surrounds the conductive pillar portion and underlies the conductive fin portion.

    Three-dimensional memory device including contact via structures for multi-level stepped surfaces and methods for forming the same
    18.
    发明授权
    Three-dimensional memory device including contact via structures for multi-level stepped surfaces and methods for forming the same 有权

    公开(公告)号：US12150300B2

    公开(公告)日：2024-11-19

    申请号：US17806390

    申请日：2022-06-10

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Yusuke Tanaka ,  Haruki Suwa

    IPC: H01L21/00 ,  H01L23/48 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing a terrace region having a plurality of steps, memory stack structures extending through the alternating stack, a retro-stepped dielectric material portion overlying the terrace region, first laterally isolated contact structures including a respective first contact via structure and a respective first dielectric spacer, and second laterally isolated contact structures including a respective second contact via structure and a respective second dielectric spacer. The respective first contact via structure contacts a top surface of a respective first electrically conductive layer in the respective step of the plurality of steps. The respective second contact via structure extends through the respective first electrically conductive layer in the respective step and contacts a top surface of a respective second electrically conductive layer which underlies the first electrically conductive layer in the respective step.

    Three-dimensional memory device with vertical word line barrier and methods for forming the same
    19.
    发明授权
    Three-dimensional memory device with vertical word line barrier and methods for forming the same 有权

    公开(公告)号：US12137565B2

    公开(公告)日：2024-11-05

    申请号：US17345831

    申请日：2021-06-11

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Fei Zhou ,  Adarsh Rajashekhar

    IPC: H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the electrically conductive layers includes a metallic fill material layer and a plurality of vertical tubular metallic liners laterally surrounding a respective one of the memory opening fill structures and located between the metallic fill material layer and a respective one of the memory opening fill structures. The tubular metallic liners may be formed by selective metal or metal oxide deposition, or by conversion of surface portions of the metallic fill material layers into metallic compound material portions by nitridation, oxidation, or incorporation of boron atoms.

    MINI-PUMP LEVEL SHIFTER FOR ROBUST SWITCHING OPERATION UNDER LOW VDD ENVIRONMENT
    20.
    发明公开
    MINI-PUMP LEVEL SHIFTER FOR ROBUST SWITCHING OPERATION UNDER LOW VDD ENVIRONMENT 审中-公开

    公开(公告)号：US20240364338A1

    公开(公告)日：2024-10-31

    申请号：US18346344

    申请日：2023-07-03

    Applicant: SanDisk Technologies LLC

    Inventor： Alvin Joshua ,  Hardwell Chibvongodze ,  Yuki Kuniyoshi ,  Akitomo Nakayama

    IPC: H03K19/0185 ,  H03K3/356

    CPC classification number: H03K19/018521 ,  H03K3/356113

    Abstract: On memory die and other circuits, some parts may operate at a VDD logic level while other elements operate at a higher logic level, such as at or near the die's supply level VSUP. To reduce power consumption and increase operating speeds, VDD levels are moving to increasingly lower voltages. To raise the logic signal from the lower level to the higher, level shifters can be used. However, as the gap between the supply level VSUP and VDD widens, it can become difficult for a level shifter to reliably raise a logic signal operating at the VDD level to the VSUP level. The address this problem, the following introduces a small charge pump to boost the input logic signals for level shifter circuits to allow them to reliably generate an output logic signal at the VSUP level from an input logic signal at low VDD levels.

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