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    Method of forming fine pattern using block copolymer
    13.
    发明授权
    Method of forming fine pattern using block copolymer 有权
    使用嵌段共聚物形成精细图案的方法

    公开(公告)号：US08263323B2

    公开(公告)日：2012-09-11

    申请号：US12591427

    申请日：2009-11-19

    Applicant: Dong Ki Yoon ,  Shi-yong Yi ,  Seok-hwan Oh ,  Kyoung-seon Kim ,  Sang Ouk Kim ,  Seung-hak Park

    Inventor： Dong Ki Yoon ,  Shi-yong Yi ,  Seok-hwan Oh ,  Kyoung-seon Kim ,  Sang Ouk Kim ,  Seung-hak Park

    IPC: G03F7/26

    CPC classification number: G03F7/0002 ,  B81C1/00031 ,  B81C2201/0149 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/405 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139

    Abstract: A method of forming a fine pattern includes forming an organic guide layer on a substrate, forming a photoresist pattern on the organic guide layer, the photoresist pattern including a plurality of openings exposing portions of the organic guide layer, forming a material layer on the exposed portions of the organic guide layer and on the photoresist pattern, the material layer including block copolymers, and rearranging the material layer through phase separation of the block copolymers into a fine pattern layer, such that the fine pattern layer includes a plurality of first blocks and a plurality of second blocks arranged in an alternating pattern, the plurality of first blocks and the plurality of the second blocks having different repeating units of the block copolymers.

    Abstract translation: 形成精细图案的方法包括在基板上形成有机引导层，在有机引导层上形成光致抗蚀剂图案，光致抗蚀剂图案包括暴露部分有机引导层的多个开口，在暴露的 有机引导层的部分和光致抗蚀剂图案上的材料层包括嵌段共聚物，并且通过将嵌段共聚物相分离成精细图案层来重排材料层，使得精细图案层包括多个第一嵌段和 以交替图案排列的多个第二块，多个第一块和多个第二块具有不同的嵌段共聚物的重复单元。

    Method of fine patterning semiconductor device
    14.
    发明授权
    Method of fine patterning semiconductor device 有权
    精细图案化半导体器件的方法

    公开(公告)号：US07998357B2

    公开(公告)日：2011-08-16

    申请号：US12217782

    申请日：2008-07-09

    Applicant: Nam-Myun Cho ,  Myeong-Cheol Kim ,  Shi-Yong Yi ,  Young-Hoon Song ,  Young-Ju Park

    Inventor： Nam-Myun Cho ,  Myeong-Cheol Kim ,  Shi-Yong Yi ,  Young-Hoon Song ,  Young-Ju Park

    IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00

    CPC classification number: H01L21/02118 ,  H01L21/02282 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31058 ,  H01L21/312 ,  H01L21/32139 ,  H01L27/105 ,  H01L27/1052

    Abstract: For integrated circuit fabrication, at least one spacer support structure is formed in a first area over a semiconductor substrate, and a mask material is deposited on exposed surfaces of the spacer support structure and on a second area over the semiconductor substrate. A masking structure is formed on a portion of the mask material in the second area, and the mask material is patterned to form spacers on sidewalls of the spacer support structure and to form a mask pattern under the masking structure. The spacer support structure and the masking structure are comprised of respective high carbon content materials that have been spin-coated and have substantially a same etch selectivity.

    Abstract translation: 对于集成电路制造，在半导体衬底上的第一区域中形成至少一个间隔件支撑结构，并且掩模材料沉积在间隔件支撑结构的暴露表面上并在半导体衬底上的第二区域上。 在第二区域中的掩模材料的一部分上形成掩模结构，并且掩模材料被图案化以在间隔物支撑结构的侧壁上形成间隔物，并在掩模结构下方形成掩模图案。 间隔物支撑结构和掩蔽结构由已经旋涂并具有基本上相同蚀刻选择性的相应的高碳含量材料构成。

    Method of fine patterning semiconductor device
    16.
    发明授权
    Method of fine patterning semiconductor device 有权
    精细图案化半导体器件的方法

    公开(公告)号：US08334089B2

    公开(公告)日：2012-12-18

    申请号：US13239555

    申请日：2011-09-22

    Applicant: Shi-Yong Yi ,  Kyoung-Taek Kim ,  Hyun-Woo Kim ,  Dong-Ki Yoon

    Inventor： Shi-Yong Yi ,  Kyoung-Taek Kim ,  Hyun-Woo Kim ,  Dong-Ki Yoon

    IPC: G03F7/00 ,  G03F7/004 ,  G03F7/20 ,  G03F7/40

    CPC classification number: H01L21/0332 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139

    Abstract: For patterning during integrated circuit fabrication, an image layer is activated for forming a respective first type polymer block at each of two nearest activated areas. A layer of block copolymer is formed on the image layer, and a plurality of the first type polymer blocks and a plurality of second and third types of polymer blocks are formed on an area of the image layer between outer edges of the two nearest activated areas, from the block copolymer. At least one of the first, second, and third types of polymer blocks are removed to form a variety of mask structures.

    Abstract translation: 对于在集成电路制造期间的图案化，图像层被激活用于在两个最近的激活区域中的每一个处形成相应的第一类型聚合物块。 在图像层上形成一层嵌段共聚物，多个第一类聚合物嵌段和多个第二和第三类聚合物嵌段形成在图像层的两个最近活化区域的外边缘之间的区域上 ，来自嵌段共聚物。 第一，第二和第三类型的聚合物嵌段中的至少一种被去除以形成各种掩模结构。

    Method of fine patterning semiconductor device
    17.
    发明授权
    Method of fine patterning semiconductor device 有权
    精细图案化半导体器件的方法

    公开(公告)号：US08053163B2

    公开(公告)日：2011-11-08

    申请号：US12283449

    申请日：2008-09-12

    Applicant: Shi-Yong Yi ,  Kyoung-Taek Kim ,  Hyun-Woo Kim ,  Dong-Ki Yoon

    Inventor： Shi-Yong Yi ,  Kyoung-Taek Kim ,  Hyun-Woo Kim ,  Dong-Ki Yoon

    IPC: G03F7/00 ,  G03F7/004 ,  G03F7/20

    CPC classification number: H01L21/0332 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139

    Abstract: For patterning during integrated circuit fabrication, an image layer is activated for forming a respective first type polymer block at each of two nearest activated areas. A layer of block copolymer is formed on the image layer, and a plurality of the first type polymer blocks and a plurality of second and third types of polymer blocks are formed on an area of the image layer between outer edges of the two nearest activated areas, from the block copolymer. At least one of the first, second, and third types of polymer blocks are removed to form a variety of mask structures.

    Abstract translation: 对于在集成电路制造期间的图案化，图像层被激活用于在两个最近的激活区域中的每一个处形成相应的第一类型聚合物块。 在图像层上形成一层嵌段共聚物，多个第一类聚合物嵌段和多个第二和第三类聚合物嵌段形成在图像层的两个最近活化区域的外边缘之间的区域上 ，来自嵌段共聚物。 第一，第二和第三类型的聚合物嵌段中的至少一种被去除以形成各种掩模结构。

    Method of fine patterning semiconductor device
    18.
    发明申请
    Method of fine patterning semiconductor device 有权
    精细图案化半导体器件的方法

    公开(公告)号：US20090176376A1

    公开(公告)日：2009-07-09

    申请号：US12217784

    申请日：2008-07-09

    Applicant: Shi-Yong Yi ,  Myeong-Cheol Kim ,  Dong-Ki Yoon ,  Kyung-Yub Jeon ,  Ji-Hoon Cha

    Inventor： Shi-Yong Yi ,  Myeong-Cheol Kim ,  Dong-Ki Yoon ,  Kyung-Yub Jeon ,  Ji-Hoon Cha

    IPC: H01L21/308

    CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/312 ,  H01L21/32139

    Abstract: For patterning during integrated circuit fabrication, a first pattern of first masking structures is formed, and a buffer layer is formed on exposed surfaces of the first masking structures. Also, a second pattern of second masking structures is formed in recesses between the buffer layer at sidewalls of the first masking structures. Furthermore, the first and masking structures are formed from spin-coating respective high carbon containing materials. Such first and second masking structures pattern a target layer with higher pitch than possible with traditional photolithography.

    Abstract translation: 为了在集成电路制造期间进行图案化，形成第一掩模结构的第一图案，并且在第一掩模结构的暴露表面上形成缓冲层。 此外，在第一掩蔽结构的侧壁处的缓冲层之间的凹部中形成第二掩模结构的第二图案。 此外，第一掩模结构和掩模结构由各自含高含碳材料的旋涂形成。 这样的第一和第二掩模结构以比传统光刻法更高的间距对目标层进行图案化。

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