公开(公告)号：US07495267B2

公开(公告)日：2009-02-24

申请号：US11409405

申请日：2006-04-21

Applicant: Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

Inventor： Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

IPC: H01L31/0368

CPC classification number: H01L29/78 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/76232 ,  H01L29/7846

Abstract: A semiconductor structure including a highly strained selective epitaxial top layer suitable for use in fabricating a strained channel transistor. The top layer is deposited on the uppermost of a series of one or more lower layers. The lattice of each layer is mismatched with the lattice of its subjacent layer by an amount not less than the lattice mismatch between the lowest layer of the series and a substrate on which it resides. A trench is formed in the uppermost series layer. The trench has rounded corners so that a dielectric material filling the trench conforms to the round corners. The rounded corners are produced by heating the uppermost series layer after trench formation.

Abstract translation: 包括适用于制造应变通道晶体管的高应变选择性外延顶层的半导体结构。 顶层沉积在一系列一个或多个下层的最上面。 每个层的晶格与其下层的晶格不匹配，其量不小于该系列的最低层与其所在的衬底之间的晶格失配。 沟槽形成在最上层的层中。 沟槽具有圆角，使得填充沟槽的电介质材料符合圆角。 通过在沟槽形成之后加热最上面的串联层来产生圆角。

公开(公告)号：US20080290421A1

公开(公告)日：2008-11-27

申请号：US11807127

申请日：2007-05-25

Applicant: Ching-Ya Wang ,  Chung-Hu Ke ,  Wen-Chin Lee

Inventor： Ching-Ya Wang ,  Chung-Hu Ke ,  Wen-Chin Lee

IPC: H01L29/94 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/76844 ,  H01L21/7685 ,  H01L29/665 ,  H01L29/66515 ,  H01L29/6659 ,  H01L29/7833

Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.

Abstract translation: 半导体结构包括半导体衬底; 半导体衬底上的栅极电介质; 位于栅极电介质上的栅电极; 与栅极电介质相邻的源极/漏极区域; 源/漏区上的硅化物区; 硅化物区域的顶部和物理接触处的金属层; 金属层上的层间电介质（ILD）; 和ILD的接触开口。 金属层通过接触开口露出。 金属层进一步在ILD下延伸。 半导体结构还包括接触开口中的接触。

公开(公告)号：US07429975B2

公开(公告)日：2008-09-30

申请号：US10996419

申请日：2004-11-26

Applicant: Wen-Chin Lee ,  Shang-Hao Chen

Inventor： Wen-Chin Lee ,  Shang-Hao Chen

IPC: G09G5/00

CPC classification number: G06F3/0346 ,  G05G9/047 ,  G06F3/0362

Abstract: A magnetic oscillation metric controller with return design comprised of a scrolling wheel mechanism, a dancer, a permanent magnet, a Hall sensor and a return structure to drive the permanent magnet by oscillation of the scrolling wheel mechanism to generate signals of changed magnetic fields resulted from displacement for achieving metric control purpose; and the return structure including an elastic stick to facilitate return after lateral or longitudinal displacement.

Abstract translation: 具有返回设计的磁振荡度量控制器包括滚动轮机构，浮动机构，永磁体，霍尔传感器和返回结构，以通过滚动轮机构的振荡来驱动永磁体，以产生由 实现度量控制目的的排量 并且返回结构包括弹性棒，以便于在横向或纵向位移之后返回。

公开(公告)号：US20080185659A1

公开(公告)日：2008-08-07

申请号：US11703365

申请日：2007-02-07

Applicant: Chung-Hu Ke ,  Chih-Hsin Ko ,  Wen-Chin Lee

Inventor： Chung-Hu Ke ,  Chih-Hsin Ko ,  Wen-Chin Lee

IPC: H01L29/94 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66606 ,  H01L29/78 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device having at least one transistor covered by an ultra-stressor layer, and method for fabricating such a device. In an NMOS device, the ultra-stressor layer includes a tensile stress film over the source and drain regions, and a compressive stress film over the poly region. In a PMOS device, the ultra-stressor layer includes a compressive stress film over the source and drain regions and a tensile stress film over the poly region. In a preferred embodiment, the semiconductor device includes a PMOS transistor and an NMOS transistor forming a CMOS device and covered with an ultra stressor layer.

Abstract translation: 具有被超应力层覆盖的至少一个晶体管的半导体器件及其制造方法。 在NMOS器件中，超应力层包括源极和漏极区域上的拉伸应力膜，以及多个区域上的压应力膜。 在PMOS器件中，超应力层包括源极和漏极区域上的压缩应力膜和在多个区域上的拉伸应力膜。 在优选实施例中，半导体器件包括PMOS晶体管和形成CMOS器件并被超压应力层覆盖的NMOS晶体管。

公开(公告)号：US07394136B2

公开(公告)日：2008-07-01

申请号：US11194084

申请日：2005-07-29

Applicant: Chung-Hu Ke ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chih-Hsin Ko ,  Chenming Hu

Inventor： Chung-Hu Ke ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chih-Hsin Ko ,  Chenming Hu

IPC: H01L21/00

CPC classification number: H01L29/7846 ,  H01L21/823807 ,  H01L21/823878 ,  H01L29/1033 ,  H01L29/78 ,  H01L29/7842

Abstract: A high performance semiconductor device and the method for making same is disclosed with an improved drive current. The semiconductor device has source and drain regions built on an active region, a length of the device being different than a width thereof. One or more isolation regions are fabricated surrounding the active region, the isolation regions are then filled with an predetermined isolation material whose volume shrinkage exceeds 0.5% after an anneal process. A gate electrode is formed over the active region, and one or more dielectric spacers are made next to the gate electrode. Then, a contact etch stopper layer is put over the device, wherein the isolation regions, spacers and contact etch layer contribute to modulating a net strain imposed on the active region so as to improve the drive current.

Abstract translation: 公开了一种改进的驱动电流的高性能半导体器件及其制造方法。 半导体器件具有构建在有源区上的源极和漏极区域，器件的长度与其宽度不同。 在有源区周围制造一个或多个隔离区域，然后用退火处理后其体积收缩率超过0.5％的预定隔离材料填充隔离区域。 在有源区上形成栅电极，并且在栅电极旁边形成一个或多个电介质间隔物。 然后，接触蚀刻停止层放置在器件上，其中隔离区，间隔物和接触蚀刻层有助于调制施加在有源区上的净应变，以便改善驱动电流。

公开(公告)号：US07354830B2

公开(公告)日：2008-04-08

申请号：US11377105

申请日：2006-03-16

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liaog Yang ,  Yee-Chia Yeo

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Chenming Hu ,  Shang-Chih Chen ,  Chih-Hao Wang ,  Fu-Liaog Yang ,  Yee-Chia Yeo

IPC: H01L21/8234

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A method of fabricating an integrated circuit is provided. A first gate dielectric portion is formed on a substrate in a first transistor region. The first gate dielectric portion includes a first high-permittivity dielectric material. The first gate dielectric portion has a first equivalent silicon oxide thickness. A second gate dielectric portion is formed on the substrate in a second transistor region. The second gate dielectric portion includes the first high-permittivity dielectric material. The second gate dielectric portion has a second equivalent silicon oxide thickness. The second equivalent silicon oxide thickness is different than the first equivalent silicon oxide thickness.

Abstract translation: 提供一种制造集成电路的方法。 第一栅介质部分形成在第一晶体管区域中的衬底上。 第一栅介质部分包括第一高介电常数介电材料。 第一栅介质部分具有第一等效氧化硅厚度。 在第二晶体管区域中的衬底上形成第二栅介质部分。 第二栅介质部分包括第一高电容率介电材料。 第二栅介质部分具有第二等效氧化硅厚度。 第二等效氧化硅厚度不同于第一等效氧化硅厚度。

公开(公告)号：US20080070429A1

公开(公告)日：2008-03-20

申请号：US11567593

申请日：2006-12-06

Applicant: WEN-CHIN LEE ,  CHENG-HSIEN LIN

Inventor： WEN-CHIN LEE ,  CHENG-HSIEN LIN

IPC: H05K1/00

CPC classification number: H05K3/3442 ,  H05K2201/09181 ,  H05K2201/10636 ,  H05K2201/10727 ,  Y02P70/611 ,  Y02P70/613

Abstract: An exemplary surface mounted electronic component has block body including a bottom soldering surface, a top surface and a peripheral wall having a first peripheral wall portion and a second peripheral wall portion. The bottom soldering surface defines a first soldering area and a second soldering area. The first peripheral wall portion adjoins the first soldering area and has at least a first cutout defined between the first peripheral wall portion and the first soldering area. The second peripheral wall portion adjoins the second soldering area and has at least a second cutout defined between the second peripheral wall portion and the second soldering area. When the surface mounted electronic component is soldered, the melting solder can climb up the cutouts of the sidewall due to capillary effect and ‘chimney effect’, thereby avoiding ‘tombstoning’.

Abstract translation: 示例性的表面安装电子部件具有块体，其包括底部焊接表面，顶表面和具有第一周壁部分和第二周壁部分的周壁。 底部焊接表面限定第一焊接区域和第二焊接区域。 所述第一周壁部分邻接所述第一焊接区域，并且至少具有限定在所述第一周壁部分和所述第一焊接区域之间的第一切口。 所述第二周壁部分邻接所述第二焊接区域，并且在所述第二周壁部分和所述第二焊接区域之间具有至少第二切口。 当表面安装的电子部件被焊接时，由于毛细管效应和“烟囱效应”，熔化焊料可以爬上侧壁的切口，从而避免“墓碑”。

公开(公告)号：US07338299B1

公开(公告)日：2008-03-04

申请号：US11567593

申请日：2006-12-06

Applicant: Wen-Chin Lee ,  Cheng-Hsien Lin

Inventor： Wen-Chin Lee ,  Cheng-Hsien Lin

IPC: H01R12/00

CPC classification number: H05K3/3442 ,  H05K2201/09181 ,  H05K2201/10636 ,  H05K2201/10727 ,  Y02P70/611 ,  Y02P70/613

Abstract: An exemplary surface mounted electronic component has block body including a bottom soldering surface, a top surface and a peripheral wall having a first peripheral wall portion and a second peripheral wall portion. The bottom soldering surface defines a first soldering area and a second soldering area. The first peripheral wall portion adjoins the first soldering area and has at least a first cutout defined between the first peripheral wall portion and the first soldering area. The second peripheral wall portion adjoins the second soldering area and has at least a second cutout defined between the second peripheral wall portion and the second soldering area. When the surface mounted electronic component is soldered, the melting solder can climb up the cutouts of the sidewall due to capillary effect and ‘chimney effect’, thereby avoiding ‘tombstoning’.

Abstract translation: 示例性的表面安装电子部件具有块体，其包括底部焊接表面，顶表面和具有第一周壁部分和第二周壁部分的周壁。 底部焊接表面限定第一焊接区域和第二焊接区域。 所述第一周壁部分邻接所述第一焊接区域，并且至少具有限定在所述第一周壁部分和所述第一焊接区域之间的第一切口。 所述第二周壁部分邻接所述第二焊接区域，并且在所述第二周壁部分和所述第二焊接区域之间具有至少第二切口。 当表面安装的电子部件被焊接时，由于毛细管效应和“烟囱效应”，熔化焊料可以爬上侧壁的切口，从而避免“墓碑”。

公开(公告)号：US20070266559A1

公开(公告)日：2007-11-22

申请号：US11560787

申请日：2006-11-16

Applicant: WEN-CHIN LEE ,  CHENG-HSIEN LIN

Inventor： WEN-CHIN LEE ,  CHENG-HSIEN LIN

IPC: H01K3/10 ,  H05K3/10

CPC classification number: H05K3/4652 ,  H05K3/0035 ,  H05K3/421 ,  H05K3/429 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2203/0554 ,  H05K2203/1476 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: An exemplary method for forming stacked via-holes in a multilayer printed circuit board includes the steps of: providing a base circuit board; attaching a first copper-coated-substrate having a first substrate and a first copper layer thereon and a second copper-coated-substrate having a second substrate and a second copper layer thereon onto the base circuit board in a manner such that; forming at least one first window in the second copper layer, making at least one first hole in the second substrate through the at least one first window, forming at least one second window in the first copper layer through the at least one first hole, and making at least one second hole in the first substrate though the at least one second window, thus forming at least one part-finished stacked via-hole; and plating the at least one part-finished stacked via-hole thereby forming at least one stacked via-hole.

Abstract translation: 在多层印刷电路板中形成堆叠的通孔的示例性方法包括以下步骤：提供基底电路板; 将其上具有第一基板和第一铜层的第一铜涂覆基板和其上具有第二基板和第二铜层的第二铜涂覆基板以如下方式附接到基板电路板上; 在所述第二铜层中形成至少一个第一窗口，通过所述至少一个第一窗口在所述第二基板中形成至少一个第一孔，通过所述至少一个第一孔在所述第一铜层中形成至少一个第二窗口，以及 通过所述至少一个第二窗口在所述第一基板中形成至少一个第二孔，从而形成至少一个部分精加工的堆叠通孔; 以及对所述至少一个部分精加工的堆叠通孔进行电镀，从而形成至少一个堆叠的通孔。

公开(公告)号：US07268024B2

公开(公告)日：2007-09-11

申请号：US10999564

申请日：2004-11-29

Applicant: Yee-Chia Yeo ,  How-Yu Chen ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Fu-Liang Yang ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  How-Yu Chen ,  Chien-Chao Huang ,  Wen-Chin Lee ,  Fu-Liang Yang ,  Chenming Hu

IPC: H01L21/84

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7843 ,  H01L29/7854

Abstract: In accordance with a preferred embodiment of the present invention, a silicon-on-insulator (SOI) chip includes a silicon layer of a predetermined thickness overlying an insulator layer. A multiple-gate fully-depleted SOI MOSFET including a strained channel region is formed on a first portion of the silicon layer. A planar SOI MOSFET including a strained channel region formed on another portion of the silicon layer. For example, the planar SOI MOSFET can be a planar fully-depleted SOI (FD-SOI) MOSFET or the planar SOI MOSFET can be a planar partially-depleted SOI (PD-SOI) MOSFET.

Abstract translation: 根据本发明的优选实施例，绝缘体上硅（SOI）芯片包括覆盖在绝缘体层上的预定厚度的硅层。 在硅层的第一部分上形成包括应变沟道区的多栅极全耗尽SOI MOSFET。 包括形成在硅层的另一部分上的应变沟道区的平面SOI MOSFET。 例如，平面SOI MOSFET可以是平面全耗尽SOI（FD-SOI）MOSFET，或者平面SOI MOSFET可以是平面部分耗尽的SOI（PD-SOI）MOSFET。