公开(公告)号：US20230157004A1

公开(公告)日：2023-05-18

申请号：US18096923

申请日：2023-01-13

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Nitin K. Ingle ,  Sung-Kwan Kang

IPC: H10B12/00 ,  H01L27/12 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

CPC classification number: H10B12/30 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1222 ,  H01L27/1255 ,  H01L29/6675 ,  H01L29/42392 ,  H01L29/78672 ,  H10B12/03 ,  H10B12/05 ,  H10B12/482

Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

公开(公告)号：US20220367560A1

公开(公告)日：2022-11-17

申请号：US17741803

申请日：2022-05-11

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee

IPC: H01L27/146 ,  H01L21/02

Abstract: Memory devices and methods of manufacturing memory devices are provided. The device and methods described decrease the resistivity of word lines by forming word lines comprising low resistivity materials. The low resistivity material has a resistivity in a range of from 5 μΩcm to 100 μΩcm. Low resistivity materials may be formed by recessing the word line and selectively growing the low resistivity materials in the recessed portion of the word line. Alternatively, low resistivity materials may be formed by depositing a metal layer and silicidating the metal in the word line region and in the common source line region.

公开(公告)号：US11430801B2

公开(公告)日：2022-08-30

申请号：US17227925

申请日：2021-04-12

Applicant: APPLIED MATERIALS, INC.

Inventor： Takehito Koshizawa ,  Mukund Srinivasan ,  Tomohiko Kitajima ,  Chang Seok Kang ,  Sung-Kwan Kang ,  Gill Y. Lee ,  Susmit Singha Roy

IPC: H01L27/1157 ,  H01L27/11582

Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.

公开(公告)号：US20220262619A1

公开(公告)日：2022-08-18

申请号：US17667704

申请日：2022-02-09

Applicant: Applied Materials, Inc.

Inventor： Ning Li ,  Shuaidl Zhang ,  Mihaela A. Balseanu ,  Qi Gao ,  Rajesh Prasad ,  Tomohiko Kitajima ,  Chang Seok Kang ,  Deven Matthew Raj Mittal ,  Kyu-Ha Shim

IPC: H01L21/02

Abstract: Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800 ° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 Å/min.

公开(公告)号：US20220059555A1

公开(公告)日：2022-02-24

申请号：US17399275

申请日：2021-08-11

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima

IPC: H01L27/11524 ,  G11C16/04 ,  H01L27/11556 ,  G11C8/14

Abstract: Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating non-replacement word lines and replacement insulators. A filled slit extends through the memory stack, and there are at least two select gate for drain (SGD) isolation regions in the memory stack adjacent the filled slit. A select-gate-for-drain (SGD) cut is patterned into the top few pairs of alternating layers in the memory stacks. Through the cut opening, the sacrificial layer of the memory stacks is removed, and an insulator layer is used to fill the opening.

公开(公告)号：US10998329B2

公开(公告)日：2021-05-04

申请号：US16517956

申请日：2019-07-22

Applicant: APPLIED MATERIALS, INC.

Inventor： Takehito Koshizawa ,  Mukund Srinivasan ,  Tomohiko Kitajima ,  Chang Seok Kang ,  Sung-Kwan Kang ,  Gill Y. Lee ,  Susmit Singha Roy

IPC: H01L27/1157 ,  H01L27/11582

Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.

公开(公告)号：US20200312874A1

公开(公告)日：2020-10-01

申请号：US16833899

申请日：2020-03-30

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Mukund Srinivasan ,  Sanjay Natarajan

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/677

Abstract: Methods of manufacturing memory devices are provided. The methods decrease the thickness of the first layers and increase the thickness of the second layers. Semiconductor devices are described having a film stack comprising alternating nitride and second layers in a first portion of the device, the alternating nitride and second layers of the film stack having a nitride:oxide thickness ratio (Nf:Of); and a memory stack comprising alternating word line and second layers in a second portion of the device, the alternating word line and second layers of the memory stack having a word line:oxide thickness ratio (Wm:Om), wherein 0.1(Wm:Om)

公开(公告)号：US20250126774A1

公开(公告)日：2025-04-17

申请号：US18403930

申请日：2024-01-04

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Sony Varghese ,  Tong Liu ,  Fredrick Fishburn

IPC: H10B12/00

Abstract: Memory devices are provided which have stacked DRAM cells, resulting in an increase in DRAM cell bit-density. In a 3D DRAM with stacked unit cell layers of one or more embodiments, it is necessary to reduce the area of a unit cell in order to increase bit density per unit area for a given number of stacked cells. In one or more embodiments, n wordlines (nWL, n is an integer≥2) share a contact pad. The shared nWLs are separated by n bitlines (BLs) to assign every cell independently one WL and one BL.

公开(公告)号：US12148475B2

公开(公告)日：2024-11-19

申请号：US17705744

申请日：2022-03-28

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Qian Fu ,  Sung-Kwan Kang ,  Takehito Koshizawa ,  Fredrick Fishburn

IPC: G11C16/04 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.

公开(公告)号：US20240365551A1

公开(公告)日：2024-10-31

申请号：US18630142

申请日：2024-04-09

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Steven C. H. Hung ,  Hsueh Chung Chen ,  Naomi Yoshida ,  Sung-Kwan Kang ,  Balasubramanian Pranatharthiharan

IPC: H10B43/35 ,  H01L21/67 ,  H01L23/528 ,  H01L23/532 ,  H10B43/20

CPC classification number: H10B43/35 ,  H01L21/67161 ,  H01L23/5283 ,  H01L23/53214 ,  H01L23/53257 ,  H10B43/20

Abstract: Exemplary semiconductor structures may include a substrate. The structures may include a first layer of silicon-and-oxygen-containing material overlying the substrate. The structures may include a second layer of silicon-and-oxygen-containing material. The structures may include a first layer of metal-and-oxygen-containing material between the first layer of silicon-and-oxygen-containing material and the second layer of silicon-and-oxygen-containing material. The first layer of metal-and-oxygen-containing material may include a first metal. The structures may include a second layer of metal-and-oxygen-containing material disposed within the first layer of metal-and-oxygen-containing material. The second layer of metal-and-oxygen-containing material may include a second metal. The structures may include a gate disposed within the second layer of metal-and-oxygen-containing material.