公开(公告)号：US11587796B2

公开(公告)日：2023-02-21

申请号：US17147578

申请日：2021-01-13

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Sung-Kwan Kang

IPC: H01L21/321 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/522

Abstract: Memory devices and methods of manufacturing memory devices are provided. The device and methods described suppress oxidation of metal layers exposed to ambient oxygen. After an opening is formed, a nitridation process occurs to nitridate the surface of the exposed metal layer inside the opening. The nitridated region formed on the surface of metal layer inside the opening works as a barrier layer for oxygen diffusion. In addition, the nitridated region works as an electrode for charge trap memory cells.

公开(公告)号：US20230012819A1

公开(公告)日：2023-01-19

申请号：US17811323

申请日：2022-07-08

Applicant: Applied Materials, Inc.

Inventor： John Byron Tolle ,  Tomohiko Kitajima ,  Thomas John Kirschenheiter ,  Patricia M. Liu ,  Zuoming Zhu ,  Joe Margetis ,  Fredrick David Fishburn ,  Abdul Wahab Mohammed ,  Gill Yong Lee

IPC: H01L27/108

Abstract: Three-dimensional dynamic random-access memory (3D DRAM) structures and methods of formation of same are provided herein. In some embodiments, a 3D DRAM stack can include alternating silicon (Si) layers and silicon germanium (SiGe) layers. Each of the Si layers may have a height greater than a height of each of the SiGe layers. Methods and systems for formation of such structures are further provided.

公开(公告)号：US11515170B2

公开(公告)日：2022-11-29

申请号：US17137637

申请日：2020-12-30

Applicant: Applied Materials, Inc.

Inventor： Shishi Jiang ,  Pramit Manna ,  Bo Qi ,  Abhijit Basu Mallick ,  Rui Cheng ,  Tomohiko Kitajima ,  Harry S. Whitesell ,  Huiyuan Wang

IPC: H01L21/311 ,  H01L21/02 ,  H01L27/11551 ,  H01L27/11578

Abstract: Methods of etching film stacks to form gaps of uniform width are described. A film stack is etched through a hardmask. A conformal liner is deposited in the gap. The bottom of the liner is removed. The film stack is selectively etched relative to the liner. The liner is removed. The method may be repeated to a predetermined depth.

公开(公告)号：US20220319601A1

公开(公告)日：2022-10-06

申请号：US17705744

申请日：2022-03-28

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Qian Fu ,  Sung-Kwan Kang ,  Takehito Koshizawa ,  Fredrick Fishburn

IPC: G11C16/04 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.

公开(公告)号：US11295786B2

公开(公告)日：2022-04-05

申请号：US16779830

申请日：2020-02-03

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Sanjay Natarajan ,  Sung-Kwan Kang ,  Lequn Liu

IPC: H01L27/108 ,  H01L21/8242 ,  G11C5/06

Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

公开(公告)号：US20210257375A1

公开(公告)日：2021-08-19

申请号：US17228034

申请日：2021-04-12

Applicant: APPLIED MATERIALS, INC.

Inventor： Takehito Koshizawa ,  Mukund Srinivasan ,  Tomohiko Kitajima ,  Chang Seok Kang ,  Sung-Kwan Kang ,  Gill Y. Lee ,  Susmit Singha Roy

IPC: H01L27/1157 ,  H01L27/11582

Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.

公开(公告)号：US20210233918A1

公开(公告)日：2021-07-29

申请号：US17227925

申请日：2021-04-12

Applicant: APPLIED MATERIALS, INC.

Inventor： Takehito Koshizawa ,  Mukund Srinivasan ,  Tomohiko Kitajima ,  Chang Seok Kang ,  Sung-Kwan Kang ,  Gill Y. Lee ,  Susmit Singha Roy

IPC: H01L27/1157 ,  H01L27/11582

Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.

公开(公告)号：US20200373310A1

公开(公告)日：2020-11-26

申请号：US16517956

申请日：2019-07-22

Applicant: APPLIED MATERIALS, INC.

Inventor： Takehito Koshizawa ,  Mukund Srinivasan ,  Tomohiko Kitajima ,  Chang Seok Kang ,  Sung-Kwan Kang ,  Gill Y. Lee ,  Susmit Singha Roy

IPC: H01L27/1157 ,  H01L27/11582

Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.

公开(公告)号：US09362186B2

公开(公告)日：2016-06-07

申请号：US14800246

申请日：2015-07-15

Applicant: Applied Materials, Inc.

Inventor： Tomohiko Kitajima ,  Jeffrey Drue David ,  Jun Qian ,  Taketo Sekine ,  Garlen C. Leung ,  Sidney P. Huey

IPC: H01L21/66 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/67 ,  H01L21/311

CPC classification number: H01L22/26 ,  B24B37/013 ,  B24B49/105 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/67075 ,  H01L21/67092 ,  H01L21/67253 ,  H01L22/14 ,  H01L22/20 ,  H01L22/34 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method of controlling polishing includes storing a base measurement, the base measurement being an eddy current measurement of a substrate after deposition of at least one layer overlying a semiconductor wafer and before deposition of a conductive layer over the at least one layer, after deposition of the conductive layer over the at least one layer and during polishing of the conductive layer on substrate, receiving a sequence of raw measurements of the substrate from an in-situ eddy current monitoring system, normalizing each raw measurement in the sequence of raw measurement to generate a sequence of normalized measurements using the raw measurement and the base measurement, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on at least the sequence of normalized measurements.

Abstract translation: 控制抛光的方法包括：在淀积位于半导体晶片上方的至少一层之后，以及在沉积导电层之后，至少沉积一层之后，存储基底测量，基底测量是衬底的涡流测量， 在至少一层上的导电层和在衬底上的导电层的抛光期间，从原位涡流监测系统接收衬底的原始测量序列，使原始测量序列中的每个原始测量标准化以产生 使用原始测量和基础测量的归一化测量序列，以及至少基于归一化测量的序列来确定抛光终点或抛光速率的调整中的至少一个。

公开(公告)号：US20230369031A1

公开(公告)日：2023-11-16

申请号：US18127213

申请日：2023-03-28

Applicant: Applied Materials, Inc.

Inventor： Tomohiko Kitajima ,  Ning Li ,  Chang Seok Kang ,  Naomi Yoshida

IPC: H01J37/32 ,  H01L21/02 ,  H01L21/67 ,  C23C16/02 ,  C23C16/56 ,  C23C16/34 ,  C23C16/36 ,  C23C16/38

CPC classification number: H01J37/32899 ,  H01L21/0217 ,  H01L21/0234 ,  H01L21/67167 ,  C23C16/0227 ,  C23C16/56 ,  C23C16/345 ,  C23C16/36 ,  C23C16/38 ,  C23C16/342 ,  H01J2237/335 ,  H01J2237/332 ,  H01J2237/336 ,  H01J37/32816 ,  H01J2237/20278

Abstract: Methods of manufacturing memory devices are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; exposing the top surface of the film stack to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying the silicon-containing dielectric layer. The processing method is performed in a processing tool without breaking vacuum.