公开(公告)号：US20140181483A1

公开(公告)日：2014-06-26

申请号：US13724506

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： James M. O'CONNOR ,  Nuwan S. Jayasena ,  Gabriel H. Loh ,  Michael Ignatowski ,  Michael J. Schulte

IPC: G06F9/30

CPC classification number: G06F15/7821 ,  Y02D10/12 ,  Y02D10/13

Abstract: Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various computation operations. This functionality would be desired where performing the operations locally near the memory devices would allow increased performance and/or power efficiency by avoiding transmission of data across the interface to the host processor.

Abstract translation: 除了一层或多层DRAM（或其他存储器技术）之外，一些堆叠堆叠的存储器将包含逻辑层。 该逻辑层可以是与存储器管芯堆叠相关联的硅插入器上的离散逻辑管芯或逻辑。 额外的电路/功能被放置在逻辑层上以实现执行各种计算操作的功能。 通过避免通过接口向主机处理器传输数据，执行本地在存储器件附近的操作将允许提高性能和/或功率效率将需要该功能。

公开(公告)号：US20140181427A1

公开(公告)日：2014-06-26

申请号：US13724338

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nuwan S. JAYASENA ,  James M. O'Connor ,  Gabriel H. Loh ,  Michael J. Schulte ,  Bradford M. Beckmann ,  Michael Ignatowski

IPC: G06F12/00

CPC classification number: G06F9/3004 ,  G06F9/3455 ,  G06F15/7821

Abstract: Some die-stacked memories will contain a logic layer in addition to one or more layers of DRAM (or other memory technology). This logic layer may be a discrete logic die or logic on a silicon interposer associated with a stack of memory dies. Additional circuitry/functionality is placed on the logic layer to implement functionality to perform various data movement and address calculation operations. This functionality would allow compound memory operations—a single request communicated to the memory that characterizes the accesses and movement of many data items. This eliminates the performance and power overheads associated with communicating address and control information on a fine-grain, per-data-item basis from a host processor (or other device) to the memory. This approach also provides better visibility of macro-level memory access patterns to the memory system and may enable additional optimizations in scheduling memory accesses.

Abstract translation: 除了一层或多层DRAM（或其他存储器技术）之外，一些堆叠堆叠的存储器将包含逻辑层。 该逻辑层可以是与存储器管芯堆叠相关联的硅插入器上的离散逻辑管芯或逻辑。 额外的电路/功能被放置在逻辑层上以实现执行各种数据移动和地址计算操作的功能。 该功能将允许复合存储器操作 - 传达到存储器的单个请求，其表征许多数据项的访问和移动。 这消除了与从主处理器（或其他设备）到存储器的以细粒度，每数据项为基础传送地址和控制信息相关联的性能和功耗开销。 这种方法还提供了对存储器系统的宏级存储器访问模式的更好的可见性，并且可以在调度存储器访问中实现附加优化。

公开(公告)号：US20140181421A1

公开(公告)日：2014-06-26

申请号：US13725724

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： James M. O'CONNOR ,  Michael J. Schulte ,  Nuwan S. Jayasena ,  Gabriel H. Loh

IPC: G06F12/08

CPC classification number: G06F9/50 ,  G06F9/526 ,  G06F2209/521 ,  G06F2209/522

Abstract: A system includes an atomic processing engine (APE) coupled to an interconnect. The interconnect is to couple to one or more processor cores. The APE receives a plurality of commands from the one or more processor cores through the interconnect. In response to a first command, the APE performs a first plurality of operations associated with the first command. The first plurality of operations references multiple memory locations, at least one of which is shared between two or more threads executed by the one or more processor cores.

Abstract translation: 系统包括耦合到互连的原子处理引擎（APE）。 互连将耦合到一个或多个处理器内核。 APE通过互连从一个或多个处理器核接收多个命令。 响应于第一命令，APE执行与第一命令相关联的第一多个操作。 第一组多个操作引用多个存储器位置，其中至少一个在一个或多个处理器核心执行的两个或多个线程之间共享。

公开(公告)号：US20240273040A1

公开(公告)日：2024-08-15

申请号：US18390893

申请日：2023-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Ignatowski ,  Michael J. Schulte ,  Gabriel Hsiuwei Loh

IPC: G06F13/16 ,  G06F1/3234 ,  G06F3/06

CPC classification number: G06F13/1684 ,  G06F1/3275 ,  G06F3/0604 ,  G06F13/1694

Abstract: Multi-stack compute chip and memory architecture is described. In accordance with the described techniques, a package includes a plurality of computing stacks, and each computing stack includes at least one compute chip and a memory. The package also includes one or more interconnects that couple the computing stacks to at least one other computing stack for sharing the memory in a coherent fashion across the plurality of computing stacks.

公开(公告)号：US20240143056A1

公开(公告)日：2024-05-02

申请号：US18218463

申请日：2023-07-05

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ILC

Inventor： Greg SADOWSKI ,  Sriram Sundarm ,  Stephen Kushnir ,  William C. Brantley ,  Michael J. Schulte

IPC: G06F1/28 ,  G05F1/625

CPC classification number: G06F1/28 ,  G05F1/625

Abstract: A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

公开(公告)号：US09471130B2

公开(公告)日：2016-10-18

申请号：US14063194

申请日：2013-10-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Nuwan S. Jayasena ,  Michael J. Schulte

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

Abstract: The described embodiments include a computing device with an entity (a processor, a processor core, etc.) and a controller. In these embodiments, the controller, using an idle duration history, predicts a duration of a next idle period for the entity. Based on the predicted duration of the next idle period, the controller configures the entity to operate in a corresponding idle state.

Abstract translation: 所描述的实施例包括具有实体（处理器，处理器核心等）和控制器的计算设备。 在这些实施例中，控制器使用空闲持续时间历史预测实体的下一个空闲时段的持续时间。 基于下一个空闲时段的预测持续时间，控制器将该实体配置为在相应的空闲状态下工作。

公开(公告)号：US09235528B2

公开(公告)日：2016-01-12

申请号：US13725305

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Lisa R. Hsu ,  Gabriel H. Loh ,  Michael Ignatowski ,  Michael J. Schulte ,  Nuwan S. Jayasena ,  James M. O'Connor

IPC: G06F11/00 ,  G06F12/10 ,  G06F11/20 ,  G06F11/16

CPC classification number: G06F12/10 ,  G06F11/1666 ,  G06F11/2094

Abstract: A system, method, and memory device embodying some aspects of the present invention for remapping external memory addresses and internal memory locations in stacked memory are provided. The stacked memory includes one or more memory layers configured to store data. The stacked memory also includes a logic layer connected to the memory layer. The logic layer has an Input/Output (I/O) port configured to receive read and write commands from external devices, a memory map configured to maintain an association between external memory addresses and internal memory locations, and a controller coupled to the I/O port, memory map, and memory layers, configured to store data received from external devices to internal memory locations.

Abstract translation: 提供体现本发明的一些方面的用于重新映射外部存储器地址和堆叠存储器中的内部存储器位置的系统，方法和存储器件。 堆叠的存储器包括被配置为存储数据的一个或多个存储器层。 堆叠的存储器还包括连接到存储器层的逻辑层。 逻辑层具有被配置为从外部设备接收读取和写入命令的输入/输出（I / O）端口，被配置为保持外部存储器地址和内部存储器位置之间的关联的存储器映射以及耦合到I / O端口，内存映射和内存层，配置为将从外部设备接收的数据存储到内部存储器位置。

公开(公告)号：US20150155876A1

公开(公告)日：2015-06-04

申请号：US14551147

申请日：2014-11-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Michael J. Schulte ,  Gabriel H. Loh ,  Michael Ignatowski

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  G06F11/1004 ,  G06F13/1668 ,  G06F13/4234 ,  G06F15/7867 ,  G11C7/1006 ,  G11C7/1048 ,  G11C29/70 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H03K19/17776 ,  Y02D10/14 ,  Y02D10/151

Abstract: A die-stacked memory device incorporates a reconfigurable logic device to provide implementation flexibility in performing various data manipulation operations and other memory operations that use data stored in the die-stacked memory device or that result in data that is to be stored in the die-stacked memory device. One or more configuration files representing corresponding logic configurations for the reconfigurable logic device can be stored in a configuration store at the die-stacked memory device, and a configuration controller can program a reconfigurable logic fabric of the reconfigurable logic device using a selected one of the configuration files. Due to the integration of the logic dies and the memory dies, the reconfigurable logic device can perform various data manipulation operations with higher bandwidth and lower latency and power consumption compared to devices external to the die-stacked memory device.

Abstract translation: 芯片堆叠的存储器件包括可重构逻辑器件，以在执行各种数据操作操作和使用存储在管芯堆叠的存储器件中的数据的其他存储器操作中提供实现灵活性，或者导致要存储在管芯堆叠存储器件中的数据。 堆叠式存储设备。 代表可重配置逻辑器件的相应逻辑配置的一个或多个配置文件可被存储在管芯堆叠的存储器件的配置存储器中，并且配置控制器可使用所选择的一个存储器件对可重新配置的逻辑器件进行编程 配置文件。 由于逻辑管芯和存储器管芯的集成，与可堆叠存储器件外部的器件相比，可重构逻辑器件可以执行具有更高带宽和更低延迟和功耗的各种数据操作操作。

公开(公告)号：US20150121057A1

公开(公告)日：2015-04-30

申请号：US14063194

申请日：2013-10-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Nuwan S. Jayasena ,  Michael J. Schulte

IPC: G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/152 ,  Y02D10/171

Abstract: The described embodiments include a computing device with an entity (a processor, a processor core, etc.) and a controller. In these embodiments, the controller, using an idle duration history, predicts a duration of a next idle period for the entity. Based on the predicted duration of the next idle period, the controller configures the entity to operate in a corresponding idle state.

Abstract translation: 所描述的实施例包括具有实体（处理器，处理器核心等）和控制器的计算设备。 在这些实施例中，控制器使用空闲持续时间历史预测实体的下一个空闲时段的持续时间。 基于下一个空闲时段的预测持续时间，控制器将该实体配置为在相应的空闲状态下工作。

公开(公告)号：US20150067357A1

公开(公告)日：2015-03-05

申请号：US14015578

申请日：2013-08-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Nuwan S. Jayasena ,  Indrani Paul ,  Michael J. Schulte

IPC: G06F1/26

CPC classification number: G06F1/3206 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3246 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

Abstract: The present application describes embodiments of methods for tournament prediction of power gating in processing devices. Some embodiments of the method include selecting one of a plurality of predictions of a duration of a time to a power state transition of a component in a processing device. The plurality of predictions are generated using a corresponding plurality of prediction algorithms. Some embodiments of the method also include deciding whether to transition the component from a first power state to a second power state based on the selected prediction.

Abstract translation: 本申请描述了处理设备中电源门控的比赛预测方法的实施例。 该方法的一些实施例包括选择一个时间持续时间的多个预测中的一个到处理设备中的组件的功率状态转换。 使用相应的多个预测算法生成多个预测。 该方法的一些实施例还包括基于所选择的预测来决定是否将分量从第一功率状态转换到第二功率状态。