公开(公告)号：US10043572B1

公开(公告)日：2018-08-07

申请号：US15663096

申请日：2017-07-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  John J. Wuu ,  Keith Kasprak

IPC: G11C11/40 ,  G11C11/419 ,  G11C11/418 ,  G11C5/14 ,  G11C5/06

Abstract: A system and method for providing efficient power, performance and stability tradeoffs of memory accesses are described. A computing system uses a memory for storing data, and a processing unit, which generates access request. The memory stores data and includes a dummy cell between a first region and a second region. The first region and the second region operate with at least one of two operating states such as an awake state and a sleep state. The dummy cell uses two ground connections to support two separate ground references. In one example, a first ground reference is zero volts and a second ground reference is a floating node. In another example, the first ground reference is a value shared by one of the two regions and the second ground reference is the floating node.

公开(公告)号：US09373418B2

公开(公告)日：2016-06-21

申请号：US14146118

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  Stephen Kosonocky ,  Amlan Ghosh

IPC: G11C29/00 ,  G11C29/24 ,  G11C29/02 ,  G11C11/41 ,  G11C29/04 ,  G11C29/12

CPC classification number: G11C29/24 ,  G11C11/41 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/1204

Abstract: A circuit with headroom monitoring includes a memory array having memory cells, a replica array, and a built-in self test circuit. The replica array has a plurality of word lines, a plurality of bit line pairs, and memory cells located at intersections of the plurality of word lines and the plurality of bit line pairs. The memory cells are of a same type as memory cells in the memory array. The built-in self test circuit is coupled to the replica array for adding a capacitance to at least one bit line of the plurality of bit line pairs, for sensing a read time of memory cells of the replica array with the capacitance so added, and for providing a headroom signal in response to the read time.

Abstract translation: 具有净空监测的电路包括具有存储单元的存储器阵列，复制阵列和内置自测电路。 复制数组具有多个字线，多个位线对和位于多个字线和多个位线对的交点处的存储单元。 存储单元与存储器阵列中的存储单元具有相同的类型。 内置的自检电路耦合到副本阵列，用于向多个位线对中的至少一个位线添加电容，用于利用所添加的电容感测副本阵列的存储器单元的读取时间;以及 用于响应于读取时间提供净空信号。

公开(公告)号：US20150187437A1

公开(公告)日：2015-07-02

申请号：US14146118

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  Stephen Kosonocky ,  Amlan Ghosh

IPC: G11C29/12 ,  G11C29/44

CPC classification number: G11C29/24 ,  G11C11/41 ,  G11C29/028 ,  G11C2029/0409 ,  G11C2029/1204

Abstract: A circuit with headroom monitoring includes a memory array having memory cells, a replica array, and a built-in self test circuit. The replica array has a plurality of word lines, a plurality of bit line pairs, and memory cells located at intersections of the plurality of word lines and the plurality of bit line pairs. The memory cells are of a same type as memory cells in the memory array. The built-in self test circuit is coupled to the replica array for adding a capacitance to at least one bit line of the plurality of bit line pairs, for sensing a read time of memory cells of the replica array with the capacitance so added, and for providing a headroom signal in response to the read time.

Abstract translation: 具有净空监测的电路包括具有存储单元的存储器阵列，复制阵列和内置自测电路。 复制数组具有多个字线，多个位线对和位于多个字线和多个位线对的交点处的存储单元。 存储单元与存储器阵列中的存储单元具有相同的类型。 内置的自检电路耦合到副本阵列，用于向多个位线对中的至少一个位线添加电容，用于利用所添加的电容感测副本阵列的存储器单元的读取时间;以及 用于响应于读取时间提供净空信号。

公开(公告)号：US20140204658A1

公开(公告)日：2014-07-24

申请号：US13749672

申请日：2013-01-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John J. Wuu ,  Keith A. Kasprak ,  Russell Schreiber

IPC: G11C11/412 ,  G11C7/00

CPC classification number: G11C11/412 ,  G11C7/04

Abstract: An apparatus may comprise a memory cell configured to operate according to a voltage mode, a voltage controller coupled with the memory cell, wherein the voltage controller is configured to change the voltage mode of the memory cell between a low voltage mode and a high voltage mode, and a memory controller module coupled with the memory cell, wherein the memory controller is configured to invert a logic state stored in the memory cell based on the voltage mode.

Abstract translation: 装置可以包括被配置为根据电压模式操作的存储单元，与存储单元耦合的电压控制器，其中电压控制器被配置为在低电压模式和高电压模式之间改变存储单元的电压模式 以及与所述存储器单元耦合的存储器控​​制器模块，其中所述存储器控制器被配置为基于所述电压模式反转存储在所述存储器单元中的逻辑状态。

公开(公告)号：US20240355380A1

公开(公告)日：2024-10-24

申请号：US18582782

申请日：2024-02-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  Kyle David Whittle

IPC: G11C11/4099 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4099 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096

Abstract: A system and method for efficiently resetting data stored in a memory array are described. In various implementations, an integrated circuit includes a memory for storing data, and a processing unit that generates access requests for the data stored in the memory. When access circuitry of the memory array begins a reset operation, it reduces a power supply voltage level used by memory bit cells in a column of the array to a value less than a threshold voltage of transistors. Therefore, the p-type transistors of the bit cells do not contend with the write driver during a write operation. The access circuitry provides the reset data on the write bit lines, and asserts each of the write word lines of the memory array. To complete the write operation, the access circuitry returns the power supply voltage level from below the threshold voltage level to an operating voltage level.

公开(公告)号：US20240221805A1

公开(公告)日：2024-07-04

申请号：US18090736

申请日：2022-12-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Russell Schreiber ,  Sahilpreet Singh

IPC: G11C7/12 ,  G11C5/14 ,  G11C7/10

CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C7/1096

Abstract: A static random-access memory (SRAM) circuit includes an SRAM bitcell coupled to a word line, a bit line and a complementary bit line. A precharge circuit is coupled to the bit line and the complementary bit line and includes a precharge input. A first keeper transistor is coupled to the bit line and a second keeper transistor is coupled to the complementary bit line. A write driver circuit includes a select input receiving a select signal, a write data input, and a write data compliment input, and is operable to write a data bit to the SRAM bitcell. A combinatorial logic circuit provides a precharge signal to the precharge circuit based on the select signal and a bit line precharge signal.

公开(公告)号：US20240176514A1

公开(公告)日：2024-05-30

申请号：US18059360

申请日：2022-11-28

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Sahilpreet Singh ,  Peter Louiz Rezk Beshay ,  Russell Schreiber

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0673

Abstract: An apparatus and method for efficiently designing memory arrays in semiconductor dies. In various implementations, a memory array utilizes wake pre-charge circuitry to reduce both leakage current and a transition from an idle state. When control circuitry of the memory array determines that there are no upcoming memory accesses, it disables bit line pre-charge circuitry of columns of the array. The control circuitry enables wake pre-charge circuitry to charge the bit lines to an idle voltage level equal to a difference between the power supply voltage level and a threshold voltage of a transistor. When the control circuitry determines a memory access is pending, the control circuitry transitions the memory array to an active state. Both the amount of voltage difference and the resulting latency to charge the bit lines from the idle voltage level to the power supply reference voltage level are small.

公开(公告)号：US11907070B2

公开(公告)日：2024-02-20

申请号：US17390293

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Eric Busta ,  Michael L. Golden ,  Sean M. O′Mullan ,  James Wingfield ,  Keith A. Kasprak ,  Russell Schreiber ,  Michael Estlick

IPC: G06F11/14 ,  G06F9/30 ,  G06F9/50 ,  G06F11/07

CPC classification number: G06F11/1417 ,  G06F9/3013 ,  G06F9/5011 ,  G06F11/0772

Abstract: An integrated circuit includes one or more processing units that execute instructions that employ a register file, control logic creates a pre-startup register free list, prior to normal operation of at least one of the processing units, that includes a list of registers devoid of defective registers. In some implementations, no column and row repair information is provided to register file repair logic. In certain examples, the register file is configured as a repair-less register file. During normal operation of the one or more processing units, the integrated circuit employs the pre-startup register free list to select registers in a register file for the executing instructions. Associated methods are also presented.

公开(公告)号：US20220415378A1

公开(公告)日：2022-12-29

申请号：US17359446

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Arijit Banerjee ,  John J. Wuu ,  Russell Schreiber

IPC: G11C8/16 ,  G06F30/392 ,  G11C11/419 ,  G11C11/418

Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. Adjacent bit cells in a column of an array use a split read port such that the bit cells do not share a read bit line while sharing a write bit line. The adjacent bit cells include asymmetrical read access circuits that convey data stored by latch circuitry of a corresponding bit cell to a corresponding read bit line. The layout of adjacent bit cells provides a number of contacted gate pitches per bit cell that is less than a sum of the maximum number of metal gates in layout of each of the adjacent bit cells divided by the number of adjacent bit cells.

公开(公告)号：US09575891B2

公开(公告)日：2017-02-21

申请号：US14307164

申请日：2014-06-17

Applicant: Advanced Micro Devices, Inc.

Inventor： John R. Riley ,  Russell Schreiber ,  Donald R. Weiss ,  John J. Wuu ,  William A. McGee

IPC: G06F12/00 ,  G06F12/06 ,  G11C5/02

CPC classification number: G06F12/0607 ,  G06F12/0623 ,  G06F2212/1052 ,  G06F2212/2532 ,  G11C5/025

Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M−A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle.

Abstract translation: 用于布局规划存储器的系统和方法。 计算系统包括生成存储器访问请求的处理单元和存储器。 存储器中每个存储器线的大小包括M位。 记忆体至少包括一个主要银行和一个侧边银行。 主存储体包括第一部分，存取存储器线的M位的（M-A）位。 旁边组包括存取线的M位的A位的第二部分。 主要银行和旁边银行的高度相同，如果主存储包含每个存储行中的所有M位，则低于要使用的高度。 对于存储器线路的M位的访问请求的完成在类似的时间完成，例如相同的时钟周期。