公开(公告)号：US5084408A

公开(公告)日：1992-01-28

申请号：US596294

申请日：1990-10-15

申请人： Yoshiro Baba ,  Yutaka Koshino ,  Akihiko Osawa ,  Satoshi Yanagiya

发明人： Yoshiro Baba ,  Yutaka Koshino ,  Akihiko Osawa ,  Satoshi Yanagiya

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/763

CPC分类号： H01L21/76202 ,  H01L21/76264 ,  H01L21/763 ,  H01L21/76283 ,  H01L21/76286 ,  Y10S438/978

摘要： For controlling unwanted production of crystal defects from corners of isolated regions in a complete dielectric isolation structure, after at least one trench or groove is provided through a mask of an insulating film in a semiconductor substrate adhered to an insulating film of a base substrate, the mask is side-etched and the insulating film of the base substrate is selectively etched at the same time to expose corners of the semiconductor substrate. The exposed corners of the semiconductor substrate is then subjected to isotropic etching to remove a pointed portion therefrom. Thereafter, side surfaces of the semiconductor substrate exposed within the trench is oxidized to provide an insulating film for dielectric isolation which has rounded corners.

公开(公告)号：US5029324A

公开(公告)日：1991-07-02

申请号：US512013

申请日：1990-04-16

申请人： Akihiko Osawa ,  Yutaka Koshino ,  Yoshiro Baba

发明人： Akihiko Osawa ,  Yutaka Koshino ,  Yoshiro Baba

IPC分类号： H01L21/60 ,  H01L21/314 ,  H01L21/768 ,  H01L23/29 ,  H01L23/522 ,  H01L23/532 ,  H01L29/06 ,  H01L29/40

CPC分类号： H01L29/408 ,  H01L23/29 ,  H01L23/53271 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05686 ,  H01L2224/451 ,  H01L2224/48463 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/13091 ,  H01L2924/3025

摘要： A semiconductor device has a semiconductor region, an electrode layer formed over the semiconductor region, and a protection layer formed to cover the semiconductor region and the electrode layer. In the semiconductor device, the protection layer is a semiconductor protection layer. Part of the semiconductive protection layer is formed thin so as to have a low resistance, permitting a corresponding portion of the electrode layer to be connected to an external bonding wire.

公开(公告)号：US6031276A

公开(公告)日：2000-02-29

申请号：US950841

申请日：1997-10-15

申请人： Akihiko Osawa ,  Yoshiro Baba ,  Masanobu Tsuchitani ,  Shizue Hori

发明人： Akihiko Osawa ,  Yoshiro Baba ,  Masanobu Tsuchitani ,  Shizue Hori

IPC分类号： H01L29/74 ,  H01L21/265 ,  H01L21/266 ,  H01L21/322 ,  H01L21/329 ,  H01L29/32 ,  H01L29/861 ,  H01L26/30

CPC分类号： H01L29/66136 ,  H01L21/26506 ,  H01L21/266 ,  H01L29/32

摘要： A semiconductor device includes a plurality of defect layers separated from one another in the semiconductor layer. A distance separating any adjacent ones of the defect layers is kept such that they are prevented from contacting each other and those regions having effect of shortening a carrier lifetime overlap each other.

摘要翻译： 半导体器件包括在半导体层中彼此分离的多个缺陷层。 保持分离任何相邻的缺陷层的距离使得它们被防止彼此接触，并且那些具有缩短载流子寿命的作用的那些区域彼此重叠。

公开(公告)号：US5242845A

公开(公告)日：1993-09-07

申请号：US866418

申请日：1992-04-10

申请人： Yoshiro Baba ,  Shunichi Hiraki ,  Akihiko Osawa ,  Satoshi Yanagiya

发明人： Yoshiro Baba ,  Shunichi Hiraki ,  Akihiko Osawa ,  Satoshi Yanagiya

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/402 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/7813 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/7831

摘要： A vertical MOS transistor comprises a semiconductor substrate, a first impurity region defined on the surface of the semiconductor substrate, a second impurity region defined under the first impurity region, the conduction type of the second impurity region being opposite to that of the first impurity region, a trench engraved on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region, and a gate electrode disposed in the trench with a gate insulation film interposing between the wall of the trench and the gate electrode. The gate insulation film is thicker on the bottom of the trench and on part of the side walls of the trench continuous to the bottom than on the other parts.

摘要翻译： 垂直MOS晶体管包括半导体衬底，限定在半导体衬底的表面上的第一杂质区域，限定在第一杂质区域下方的第二杂质区域，第二杂质区域的导电类型与第一杂质区域的导电类型相反 刻蚀在所述半导体衬底的表面上的沟槽，以切割穿过所述第一和第二杂质区域至少比所述第二杂质区域的底部更深;以及栅电极，设置在所述沟槽中，栅极绝缘膜插入在所述第二杂质区域的壁之间 沟槽和栅电极。 栅极绝缘膜在沟槽的底部和沟槽的侧壁的一部分比底部更厚，而不是其它部分。

公开(公告)号：US5126807A

公开(公告)日：1992-06-30

申请号：US713505

申请日：1991-06-12

申请人： Yoshiro Baba ,  Shunichi Hiraki ,  Akihiko Osawa ,  Satoshi Yanagiya

发明人： Yoshiro Baba ,  Shunichi Hiraki ,  Akihiko Osawa ,  Satoshi Yanagiya

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/402 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813

摘要： A vertical MOS transistor comprises a semiconductor substrate, a first impurity region defined on the surface of the semiconductor substrate, a second impurity region defined under the first impurity region, the conduction type of the second impurity region being opposite to that of the first impurity region, a trench engraved on the surface of the semiconductor substrate to cut through the first and second impurity regions deeper than at least the bottom of the second impurity region, and a gate electrode disposed in the trench with a gate insulation film interposing between the wall of the trench and the gate electrode. THE gate insulation film is thicker on the bottom of the trench and on part of the side walls of the trench continuous to the bottom than on the other parts.

摘要翻译： 垂直MOS晶体管包括半导体衬底，限定在半导体衬底的表面上的第一杂质区域，限定在第一杂质区域下方的第二杂质区域，第二杂质区域的导电类型与第一杂质区域的导电类型相反 刻蚀在所述半导体衬底的表面上的沟槽，以切割穿过所述第一和第二杂质区域至少比所述第二杂质区域的底部更深;以及栅电极，设置在所述沟槽中，栅极绝缘膜插入在所述第二杂质区域的壁之间 沟槽和栅电极。 栅极绝缘膜在沟槽的底部和沟槽的侧壁的一部分比底部的部分更厚，而不是其他部分。

公开(公告)号：US6084263A

公开(公告)日：2000-07-04

申请号：US27727

申请日：1998-02-23

申请人： Masanobu Tsuchitani ,  Shizue Hori ,  Akihiko Osawa

发明人： Masanobu Tsuchitani ,  Shizue Hori ,  Akihiko Osawa

IPC分类号： H01L29/861 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7395 ,  H01L29/0611

摘要： The main characteristic feature of the invention is to prevent a leakage current from flowing when a planar type semiconductor device having a high breakdown voltage is reverse-biased. For example, a semiconductive film is formed on the surface of an n-type Si substrate between a second p-type base layer selectively formed on the surface of the Si substrate and a channel stop layer formed to surround the second p-type base layer at a predetermined interval. The dangling bond density of the semiconductive film is set at 1.25.times.1018 cm.sup.-3. With this structure, the discrete level in the band gap approach a continuum, and the time required to populate the trapping level in the semiconductive film with carriers is shortened.

摘要翻译： 本发明的主要特征是当具有高击穿电压的平面型半导体器件被反向偏置时，防止漏电流流动。 例如，在n型Si衬底的表面上形成半导体膜，该第二p型基极层选择性地形成在Si衬底表面上的第二p型基极层和形成为围绕第二p型基极层的沟道阻挡层 以预定间隔。 半导体膜的悬挂键密度设定为1.25×10 18 cm -3。 利用这种结构，带隙中的离散水平接近连续体，缩短了用载体填充半导体薄膜中的捕获水平所需的时间。

公开(公告)号：US07227223B2

公开(公告)日：2007-06-05

申请号：US10618624

申请日：2003-07-15

申请人： Noboru Matsuda ,  Hitoshi Kobayashi ,  Masaru Kawakatsu ,  Akihiko Osawa

发明人： Noboru Matsuda ,  Hitoshi Kobayashi ,  Masaru Kawakatsu ,  Akihiko Osawa

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/41766 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/7802

摘要： A semiconductor device, and particularly an MOS transistor device, wherein in order to increase a channel region density and to achieve a low resistance of a transistor device there is provided a first gate electrode group having a plurality of gate electrodes formed on a semiconductor substrate to be away from each other at first equal spacings, a second gate electrode group having a plurality of gate electrodes formed on the semiconductor substrate to be away from each other at the first equal spacings, a source contact portion formed away from the first or the second gate electrode group at a second spacing, and source regions for electrically interconnecting the first gate electrode group and the source contact. The source regions are connected to each other at one end of the first gate electrode group, and separated at the other end of the first gate electrode group. In addition, the gate electrodes of the first group are connected each other at the other end. The second spacing is greater than the first spacing.

摘要翻译： 一种半导体器件，特别是MOS晶体管器件，其中为了增加沟道区密度并实现晶体管器件的低电阻，提供了一种第一栅极电极组，其具有形成在半导体衬底上的多个栅极电极 在第一等间隔处彼此远离的第二栅极电极组，具有形成在半导体衬底上的多个栅电极以彼此间隔开的第一等间距彼此远离的第二栅电极组;远离第一或第二 第二间隔的栅极电极组和用于将第一栅极电极组和源极接触电互连的源极区域。 源极区域在第一栅电极组的一端彼此连接，并在第一栅电极组的另一端分离。 此外，第一组的栅电极在另一端彼此连接。 第二个间距大于第一个间距。

公开(公告)号：US06740931B2

公开(公告)日：2004-05-25

申请号：US10417110

申请日：2003-04-17

申请人： Shigeo Kouzuki ,  Hideki Okumura ,  Hitoshi Kobayashi ,  Satoshi Aida ,  Masaru Izumisawa ,  Akihiko Osawa

发明人： Shigeo Kouzuki ,  Hideki Okumura ,  Hitoshi Kobayashi ,  Satoshi Aida ,  Masaru Izumisawa ,  Akihiko Osawa

IPC分类号： H01L2994

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696

摘要： A semiconductor device which comprises a semiconductor substrate, semiconductor pillar regions each having first and second semiconductor pillar portions, the second semiconductor pillar portion being sandwiched by the first semiconductor pillar portions, a base layer formed in the second semiconductor pillar portion, a source diffusion layer formed in the base layer, a gate insulating film formed on a portion of the base layer, a gate electrode formed on the gate insulating film, and isolation regions which isolates the semiconductor pillar regions from each other and are formed in trenches between the semiconductor pillar regions, wherein each of the isolation regions comprises an oxide film formed on an inner surface of the trench and a nitride film formed on the oxide film, the nitride film being filled in the trench, and a film thickness ratio of the oxide film and the nitride film is in a range of 2:1 to 5:1.

公开(公告)号：US20060145290A1

公开(公告)日：2006-07-06

申请号：US11294411

申请日：2005-12-06

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

IPC分类号： H01L29/00 ,  H01L21/425 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/7802

摘要： A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.

公开(公告)号：US06995426B2

公开(公告)日：2006-02-07

申请号：US10327937

申请日：2002-12-26

申请人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

发明人： Hideki Okumura ,  Hitoshi Kobayashi ,  Masanobu Tsuchitani ,  Akihiko Osawa ,  Wataru Saito ,  Masakazu Yamaguchi ,  Ichiro Omura

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/7802

摘要： A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.

摘要翻译： 半导体器件包括形成在第一导电类型的半导体层中的扩散区域。 扩散区域分别包括第一和第二导电类型的第一和第二杂质扩散区域。 扩散区域具有由第一和第二杂质扩散区域的杂质浓度限定的第一和第二区域。 第一和第二区域之间的结点形成在第一和第二杂质扩散区域彼此重叠的部分中。 在第一或第二区域的半导体层的平面方向上的杂质浓度的周期小于半导体层的平面方向上的构成第一或第二区域的第一和第二杂质扩散区域的最大宽度 第二区。