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公开(公告)号：US09653079B2
公开(公告)日：2017-05-16
申请号：US14621093
申请日：2015-02-12
Applicant: Apple Inc.
Inventor： Manu Gulati , Gilbert H. Herbeck , Alexei E. Kosut , Girault W. Jones , Timothy J. Millet
CPC classification number: G10L15/28 , G10L15/08 , G10L15/22 , G10L2015/088 , G10L2015/223
Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
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12.发明授权公开(公告)号：US09619377B2
公开(公告)日：2017-04-11
申请号：US14458949
申请日：2014-08-13
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
CPC classification number: G06F12/0223 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F3/0625 , G06F3/0632 , G06F3/0634 , G06F3/0673 , G06F9/4406 , G06F12/0646 , G06F13/1668 , G06F13/4068 , G06F13/4265 , G06F2212/1032 , G11C11/40615 , Y02D10/122 , Y02D10/151 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
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公开(公告)号：US09549373B2
公开(公告)日：2017-01-17
申请号：US14444198
申请日：2014-07-28
Applicant: Apple Inc.
Inventor： Manu Gulati , Gilbert H. Herbeck
CPC classification number: H04W52/0235 , H04W52/0212 , Y02D70/00 , Y02D70/142 , Y02D70/26
Abstract: A method for managing power in a system, in which the system may include a first device configured to transmit serial data and a second device, coupled to the first device. The second device may include a transceiver and interrupt logic, and may be configured to activate the interrupt logic and enable a reduced power mode for the transceiver. Power consumption of the transceiver operating in the reduced power mode may be less than power consumption of the transceiver in an operating mode. The second device may also be configured to assert an interrupt signal responsive to a change in a voltage level of an input of the second device and then de-activate the reduced power mode for the transceiver responsive to the assertion of the interrupt signal.
Abstract translation: 一种用于管理系统中的电力的方法，其中所述系统可以包括被配置为传送串行数据的第一设备和耦合到所述第一设备的第二设备。 第二设备可以包括收发器和中断逻辑，并且可以被配置为激活中断逻辑并使能收发器的降低的功率模式。 以降低功率模式工作的收发器的功耗可能小于工作模式下收发器的功耗。 第二设备还可以被配置为响应于第二设备的输入的电压电平的变化来断言中断信号，然后响应于断言中断信号的断言而使得收发器的降低功率模式被去激活。
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公开(公告)号：US20160240193A1
公开(公告)日：2016-08-18
申请号：US14621093
申请日：2015-02-12
Applicant: Apple Inc.
Inventor： Manu Gulati , Gilbert H. Herbeck , Alexei E. Kosut , Girault W. Jones , Timothy J. Millet
CPC classification number: G10L15/28 , G10L15/08 , G10L15/22 , G10L2015/088 , G10L2015/223
Abstract: In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.
Abstract translation: 在一个实施例中，芯片上的系统（SOC）可以包括一个或多个中央处理单元（CPU），存储器控制器和被配置为当SOC的其余部分断电时保持通电的电路。 该电路可以被配置为接收音频采样并将这些音频样本与预定模式相匹配。 在SOC的其余部分断电的时间内，电路可以根据第一时钟进行操作。 响应于检测样本中的预定模式，电路可以使存储器控制器和处理器加电。 在上电过程中，具有比第一时钟具有一个或多个更好特征的第二时钟可以变得可用。 电路可以切换到第二时钟，同时保持采样，或者丢失至多一个采样，或者不超过阈值数量的采样。
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公开(公告)号：US20150346001A1
公开(公告)日：2015-12-03
申请号：US14458885
申请日：2014-08-13
Applicant: Apple Inc.
Inventor： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
CPC classification number: G01D9/00 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F13/1689 , Y02D10/122 , Y02D10/171 , Y02D50/20
Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.
Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以对所捕获的传感器数据进行过滤。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。
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Patent Agency Ranking
公开(公告)号：US20140310540A1
公开(公告)日：2014-10-16
申请号：US13861708
申请日：2013-04-12
Applicant: APPLE INC.
Inventor： Gilbert H. Herbeck
IPC: G06F1/32
CPC classification number: G06F1/3206 , G06F1/26 , G06F1/3237 , G06F1/3287 , Y02D10/128 , Y02D10/171
Abstract: A method and apparatus for power managed interrupt handling is disclosed. In one embodiment, a system includes one or more agents that may invoke an interrupt request. An interrupt controller is configured to receive and process the interrupt requests. When idle, the interrupt controller may be placed in a low power state. The system also includes an interrupt power control circuit coupled to receive interrupt request indications from each of the one or more agents that may invoke interrupts. The interrupt power control circuit is configured to assert a wakeup signal responsive to receiving an indication of an interrupt request from one of the agents. If the interrupt controller is in a low power state, it may exit the state and resume operation in an active state responsive to assertion of the wakeup signal.
Abstract translation: 公开了一种用于功率管理中断处理的方法和装置。 在一个实施例中，系统包括可以调用中断请求的一个或多个代理。 中断控制器配置为接收和处理中断请求。 当空闲时，中断控制器可能处于低功率状态。 该系统还包括中断功率控制电路，其耦合以从可调用中断的一个或多个代理中的每一个接收中断请求指示。 中断功率控制电路被配置为响应于从代理之一接收到中断请求的指示来断言唤醒信号。 如果中断控制器处于低功率状态，则它可以退出状态，并且响应于唤醒信号的断言而在有效状态下恢复操作。
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公开(公告)号：US20180107240A1
公开(公告)日：2018-04-19
申请号：US15831732
申请日：2017-12-05
Applicant: Apple Inc.
Inventor： Shu-Yi Yu , Erik P. Machnicki , Gilbert H. Herbeck , Kiran B. Kattel , Manu Gulati
IPC: G06F1/12
Abstract: In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.
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公开(公告)号：US09747239B2
公开(公告)日：2017-08-29
申请号：US14467164
申请日：2014-08-25
Applicant: Apple Inc.
Inventor： Gilbert H. Herbeck , Munetoshi Fukami , Manu Gulati
CPC classification number: G06F13/4022 , G06F1/3275 , G06F1/3296 , Y02D10/14 , Y02D10/172 , Y02D50/20
Abstract: A transaction filter for an on-chip communications network is disclosed. In one embodiment, an integrated circuit (IC) include a number of functional circuit blocks, some of which may be placed in a sleep mode (e.g., power-gated). The IC also includes a number of transaction filters that are each associated with a unique one of the functional circuit blocks. Responsive to its associated functional circuit block generating a transaction, a given transaction filter may determine whether the functional circuit block to which the transaction is destined is in a sleep mode. If it is determined that the transaction is destined for a functional circuit block that is currently in the sleep mode, the transaction filter may block the transaction from being conveyed.
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公开(公告)号：US09438256B2
公开(公告)日：2016-09-06
申请号：US14478387
申请日：2014-09-05
Applicant: Apple Inc.
Inventor： Shane J. Keil , Gilbert H. Herbeck
IPC: H03L7/00 , H03L7/091 , H03K5/1534
CPC classification number: H03L7/091 , H03K5/1534
Abstract: A method and apparatus for synchronizing data transfers from a first clock domain to a second clock domain includes sampling data from circuit included in the first clock domain. The clock signal from the first clock domain may then be synchronized to a clock signal from the second clock domain. The sampled data may then be captured using the clock signal from the second clock domain responsive to a detection of an edge of the synchronized first clock signal.
Abstract translation: 用于将从第一时钟域到第二时钟域的数据传输同步的方法和装置包括从包括在第一时钟域中的电路的采样数据。 然后可以将来自第一时钟域的时钟信号与来自第二时钟域的时钟信号同步。 然后可以利用来自第二时钟域的时钟信号来捕获采样数据，以响应于同步的第一时钟信号的边沿的检测。
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公开(公告)号：US20160218721A1
公开(公告)日：2016-07-28
申请号：US14608107
申请日：2015-01-28
Applicant: Apple Inc.
Inventor： Gilbert H. Herbeck
IPC: H03L7/08
CPC classification number: H03L7/0802 , G06F1/04 , G06F1/08 , G06F1/324
Abstract: A system may include a processor, a first clock source generating a first clock signal, a second clock source generating a second clock signal, and a clock generation unit. In a first closed-loop mode of operation, the clock generation unit may be configured to generate a system clock signal at a target frequency by comparing the system clock signal to the first clock signal. The clock generation unit may be configured to generate the system clock signal in an open-loop mode of operation in response to a transition in a control signal. The clock generation unit may be configured to operate in a second closed-loop mode of operation after operating in the open-loop mode of operation, wherein the clock generation unit is configured to generate the system clock signal at substantially the same target frequency by comparing the system clock signal to the second clock signal.
Abstract translation: 系统可以包括处理器，产生第一时钟信号的第一时钟源，产生第二时钟信号的第二时钟源和时钟产生单元。 在第一闭环操作模式中，时钟生成单元可以被配置为通过将系统时钟信号与第一时钟信号进行比较来产生目标频率的系统时钟信号。 时钟生成单元可以被配置为响应于控制信号中的转变而以开环操作模式生成系统时钟信号。 时钟生成单元可以被配置为在开环操作模式下操作之后以第二闭环操作模式操作，其中时钟生成单元被配置为通过比较产生基本上相同的目标频率的系统时钟信号 系统时钟信号到第二个时钟信号。
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