公开(公告)号：US20190237111A1

公开(公告)日：2019-08-01

申请号：US15881704

申请日：2018-01-26

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Satinderjit Singh ,  Abhishek B. Akkur ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Jungtae Kwon ,  Jitendra Dasani ,  Manoj Puthan Purayil

IPC: G11C5/06 ,  G11C7/06

CPC classification number: G11C5/063 ,  G11C7/06

Abstract: Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines.

公开(公告)号：US11664086B2

公开(公告)日：2023-05-30

申请号：US17375887

申请日：2021-07-14

Applicant: Arm Limited

Inventor： Yew Keong Chong ,  Andy Wangkun Chen ,  Bikas Maiti ,  Vivek Nautiyal

IPC: G11C29/00 ,  G11C7/10 ,  G11C29/18

CPC classification number: G11C29/76 ,  G11C7/1012 ,  G11C29/18 ,  G11C29/785 ,  G11C2029/1802

Abstract: Various implementations described herein are directed to a device having memory architecture with an array of memory cells arranged in multiple columns with redundancy including first columns of memory cells disposed in a first region along with second columns of memory cells and redundancy columns of memory cells disposed in a second region that is laterally opposite the first region. The device may have column shifting logic that is configured to receive data from the multiple columns, shift the data from the first columns in the first region to a first set of the redundancy columns in the second region, and shift data from the second columns in the second region to a second set of the redundancy columns in the second region.

公开(公告)号：US20190237135A1

公开(公告)日：2019-08-01

申请号：US15886630

申请日：2018-02-01

Applicant: Arm Limited

Inventor： Arjunesh Namboothiri Madhavan ,  Akash Bangalore Srinivasa ,  Sujit Kumar Rout ,  Vikash ,  Gaurav Rattan Singla ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Jitendra Dasani ,  Lalit Gupta

IPC: G11C11/419 ,  H01L29/94 ,  H01L27/11 ,  G11C7/12 ,  G11C7/18 ,  G11C8/16 ,  G11C7/10

CPC classification number: G11C11/419 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/18 ,  G11C8/16 ,  H01L27/1116 ,  H01L29/94

Abstract: Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.

公开(公告)号：US20190198064A1

公开(公告)日：2019-06-27

申请号：US15851341

申请日：2017-12-21

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C7/08 ,  G11C7/22 ,  G11C7/12

Abstract: Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.

公开(公告)号：US20190122724A1

公开(公告)日：2019-04-25

申请号：US15789715

申请日：2017-10-20

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Fakhruddin Ali Bohra

IPC: G11C11/418 ,  G11C11/412 ,  H01L27/11 ,  H01L23/528

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to multiple dummy wordline loads via a dummy wordline. The integrated circuit may include demultiplexer circuitry coupled to a first path of the dummy wordline between the dummy wordline driver and the multiple dummy wordline loads. The integrated circuit may include multiplexer circuitry coupled to a second path of the dummy wordline between the multiple dummy wordline loads and a dummy bitline load. The demultiplexer circuitry and the multiplexer circuitry may be controlled with one or more selection signals to select at least one of the multiple dummy wordline loads.

公开(公告)号：US20190057735A1

公开(公告)日：2019-02-21

申请号：US15679325

申请日：2017-08-17

Applicant: ARM Limited

Inventor： Abhishek B. Akkur ,  Jitendra Dasani ,  Shri Sagar Dwivedi ,  Vivek Nautiyal ,  Satinderjit Singh ,  Vasimraja Bhavikatti

IPC: G11C11/419 ,  H01L23/528 ,  G06F17/50 ,  H01L27/11

Abstract: A circuit includes a dummy wordline, a dummy bitline, and a dummy cell coupled to the dummy bitline. The dummy cell includes an active pulldown nMOSFET and a pass nMOSFET having a gate connected to the dummy wordline, a first source terminal connected to the drain terminal of the active pulldown nMOSFET, and a drain terminal connected to the dummy bitline. The circuit further includes a substrate-connected dummy bitline coupled to the source terminal of each active pulldown nMOSFET and coupled to a substrate.

公开(公告)号：US20180331681A1

公开(公告)日：2018-11-15

申请号：US16042949

申请日：2018-07-23

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Vivek Nautiyal ,  Andy Wangkun Chen ,  Jitendra Dasani ,  Bo Zheng ,  Akshay Kumar ,  Vivek Asthana

IPC: H03K17/22 ,  G11C5/14

CPC classification number: H03K17/223 ,  G11C5/148

Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

公开(公告)号：US10074410B2

公开(公告)日：2018-09-11

申请号：US15282532

申请日：2016-09-30

Applicant: ARM Limited

Inventor： Vivek Nautiyal ,  Jitendra Dasani ,  Fakhruddin Ali Bohra ,  Satinderjit Singh ,  Shri Sagar Dwivedi

IPC: G11C7/22 ,  G11C7/12 ,  G11C5/14 ,  G11C8/08

CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C7/22 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18

Abstract: Various implementations described herein may refer to and may be directed to an integrated circuit using shaping and timing circuitries. In one implementation, an integrated circuit may include memory that is accessed based on a voltage level on a first control line, and may include a control driver circuitry coupled to the first and a second control line that drives a first and a second control signal toward first or second voltage levels. The integrated circuit may include a shaper circuitry coupled to the control lines that includes a first clamping transistor that couples the first control line to a timed supply node in response to the driving of the second control signal toward the first voltage. The integrated circuit may include a timing circuitry coupled to the first shaper circuitry that includes a header transistor that couples the timed supply node to a voltage supply source.

公开(公告)号：US10033376B2

公开(公告)日：2018-07-24

申请号：US15143197

申请日：2016-04-29

Applicant: ARM Limited

Inventor： Lalit Gupta ,  Vivek Nautiyal ,  Andy Wangkun Chen ,  Jitendra Dasani ,  Bo Zheng ,  Akshay Kumar ,  Vivek Asthana

IPC: H03L7/00 ,  H03K17/22 ,  G11C5/14

Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.

公开(公告)号：US20180096715A1

公开(公告)日：2018-04-05

申请号：US15282532

申请日：2016-09-30

Applicant: ARM Limited

Inventor： Vivek Nautiyal ,  Jitendra Dasani ,  Fakhruddin Ali Bohra ,  Satinderjit Singh ,  Shri Sagar Dwivedi

IPC: G11C7/12 ,  G11C5/14 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C5/147 ,  G11C7/22 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C8/18

Abstract: Various implementations described herein may refer to and may be directed to an integrated circuit using shaping and timing circuitries. In one implementation, an integrated circuit may include memory that is accessed based on a voltage level on a first control line, and may include a control driver circuitry coupled to the first and a second control line that drives a first and a second control signal toward first or second voltage levels. The integrated circuit may include a shaper circuitry coupled to the control lines that includes a first clamping transistor that couples the first control line to a timed supply node in response to the driving of the second control signal toward the first voltage. The integrated circuit may include a timing circuitry coupled to the first shaper circuitry that includes a header transistor that couples the timed supply node to a voltage supply source.