公开(公告)号：US07344905B2

公开(公告)日：2008-03-18

申请号：US10824838

申请日：2004-04-15

申请人： Peidong Wang ,  Chih-Cheng Lu ,  Daryoosh Vakhshoori

发明人： Peidong Wang ,  Chih-Cheng Lu ,  Daryoosh Vakhshoori

IPC分类号： H01L21/00

CPC分类号： B82Y20/00 ,  H01S5/028 ,  H01S5/06255 ,  H01S5/101 ,  H01S5/1057 ,  H01S5/34 ,  H01S5/3413 ,  H01S2301/04

摘要： Semiconductor substrate is disclosed having quantum wells having first bandgap, and quantum wells having second bandgap less than second bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells having given bandgap, other quantum wells modified to bandgap greater than given bandgap. Semiconductor substrate is disclosed comprising wafer having quantum wells, section of first bandgap, and section of second bandgap greater than first bandgap. Method for forming semiconductor substrate is provided, comprising providing wafer having given bandgap, depositing dielectric cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells modified by depositing cap and rapid thermal annealing to tuned bandgap greater than given bandgap. Method for forming semiconductor substrate is disclosed, comprising providing wafer having quantum wells having given bandgap, depositing cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap.

摘要翻译： 公开了具有量子阱具有第一带隙的半导体衬底，以及具有小于第二带隙的第二带隙的量子阱。 公开了半导体结构，其包括具有给定带隙的量子阱的衬底，其他量子阱被修改为具有大于给定带隙的带隙。 公开了半导体衬底，其包括具有量子阱的晶片，第一带隙的截面以及大于第一带隙的第二带隙的截面。 提供了形成半导体衬底的方法，其包括提供具有给定带隙的晶片，在部分上沉积介电帽和快速热退火至大于给定带隙的调谐带隙。 公开了半导体结构，其包括具有通过沉积帽和快速热退火而修改的量子阱的衬底，所述量子阱具有大于给定带隙的调谐带隙。 公开了一种用于形成半导体衬底的方法，其包括提供具有给定带隙的量子阱的晶片，将部分上的沉积帽和快速热退火至大于给定带隙的调谐带隙。

公开(公告)号：US20070073184A1

公开(公告)日：2007-03-29

申请号：US11534807

申请日：2006-09-25

申请人： Chih-Cheng Lu ,  Gin-Shin Chen ,  Sheng-Fu Chen ,  Ming-Shaung Ju ,  Chou-Ching Lin

发明人： Chih-Cheng Lu ,  Gin-Shin Chen ,  Sheng-Fu Chen ,  Ming-Shaung Ju ,  Chou-Ching Lin

IPC分类号： A61B5/04

CPC分类号： A61B5/0478 ,  A61B5/7239 ,  A61B2562/046

摘要： A sensor device that detects Laplacian electroencephalogram (LEEG) signals includes a signal acquisition module placed on a scalp of a subject to acquire brain signals. A signal processor is coupled or connected to the signal acquisition module to perform a Laplacian operation on the signals acquired by the signal acquisition module such that the noise signal is reduced to yield an analog LEEG signal with a high signal-to-noise (S/N) ratio.

摘要翻译： 检测拉普拉斯脑电图（LEEG）信号的传感器装置包括放置在受试者头皮上的信号采集模块以获取脑信号。 信号处理器被耦合或连接到信号采集模块，以对由信号采集模块获取的信号执行拉普拉斯算子，使得降低噪声信号以产生具有高信噪比的模拟LEEG信号（S / N）比。

公开(公告)号：US07118987B2

公开(公告)日：2006-10-10

申请号：US10767657

申请日：2004-01-29

申请人： Chu-Yun Fu ,  Chih-Cheng Lu ,  Syun-Ming Jang

发明人： Chu-Yun Fu ,  Chih-Cheng Lu ,  Syun-Ming Jang

IPC分类号： H01L21/76

CPC分类号： H01L21/76235 ,  A61F2/958 ,  A61F2002/9583 ,  A61F2250/0098 ,  A61M25/001 ,  A61M25/005 ,  A61M25/0054 ,  A61M25/0068 ,  A61M25/0069 ,  A61M25/008 ,  A61M25/0108 ,  A61M25/0127 ,  A61M25/1027 ,  A61M2025/1079 ,  A61M2025/1093 ,  A61M2205/32

摘要： A shallow trench isolation (STI) structure and method of forming the same with reduced stress to improve charge mobility the method including providing a semiconductor substrate comprising at least one patterned hardmask layer overlying the semiconductor substrate; dry etching a trench in the semiconductor substrate according to the at least one patterned hardmask layer; forming one or more liner layers to line the trench selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride; forming one or more layers of trench filling material comprising silicon dioxide to backfill the trench; carrying out at least one thermal annealing step to relax accumulated stress in the trench filling material; carrying out at least one of a CMP and dry etch process to remove excess trench filling material above the trench level; and, removing the at least one patterned hardmask layer.

摘要翻译： 一种浅沟槽隔离（STI）结构及其形成方法，其具有减小的应力以改善电荷迁移率，该方法包括提供包括覆盖在半导体衬底上的至少一个图案化硬掩模层的半导体衬底; 根据所述至少一个图案化硬掩模层干蚀刻所述半导体衬底中的沟槽; 形成一个或多个衬垫层以使选自二氧化硅，氮化硅和氮氧化硅的沟槽的沟槽; 形成包含二氧化硅的一层或多层沟槽填充材料以回填沟槽; 进行至少一个热退火步骤以缓和沟槽填充材料中的累积应力; 执行CMP和干蚀刻工艺中的至少一个以去除沟槽高度上的多余沟槽填充材料; 以及去除所述至少一个图案化的硬掩模层。

公开(公告)号：US09709640B2

公开(公告)日：2017-07-18

申请号：US14840475

申请日：2015-08-31

申请人： Ching-Ray Chang ,  Jen-Tzong Jeng ,  Jen-Hwa Hsu ,  Chih-Cheng Lu ,  Bor-Lin Lai ,  Van-Su Luong

发明人： Ching-Ray Chang ,  Jen-Tzong Jeng ,  Jen-Hwa Hsu ,  Chih-Cheng Lu ,  Bor-Lin Lai ,  Van-Su Luong

IPC分类号： G01R33/09 ,  G01R33/00 ,  G01D5/14

CPC分类号： G01R33/09 ,  G01D5/145 ,  G01R33/0011 ,  G01R33/0094

摘要： A single bridge magnetic field sensor includes a fluxguide mounted to a surface of a substrate. A bridge unit includes first, second, third, and fourth magnetoresistive elements mounted around the fluxguide and mounted on the surface of the substrate. A switching circuit is electrically connected to two voltage inputs, two grounding terminals, two voltage output terminals, and the four magnetoresistive elements. The switching circuit can proceed with circuit switching according to a magnetic field in each axis direction to be measured, thereby changing electrical connection between the voltage inputs, the grounding terminals, the voltage output terminals, and the four magnetoresistive elements. A measuring unit is electrically connected to the two voltage output terminals and the four magnetoresistive elements. The magnetoresistances of the four magnetoresistive elements measured by the measuring unit and output voltages of the voltage output terminals can be used to obtain a magnetic field measurement result.

公开(公告)号：US20080146889A1

公开(公告)日：2008-06-19

申请号：US11637737

申请日：2006-12-13

申请人： Shuenn-Tsong Young ,  Chung-Wang Lee ,  Chih-Cheng Lu ,  Tsair Kao ,  Woei-Chyn Chu

发明人： Shuenn-Tsong Young ,  Chung-Wang Lee ,  Chih-Cheng Lu ,  Tsair Kao ,  Woei-Chyn Chu

IPC分类号： A61B5/00

CPC分类号： A61B5/0205 ,  A61B5/02438 ,  A61B5/1117 ,  A61B5/1135

摘要： In a method of monitoring human physiological parameters and safe condition universally, the method is applied to a monitoring apparatus worn at an examinee's body and includes the steps of: monitoring the examinee's current plurality of physiological parameters and plurality of movement information; analyzing the movement information to determine whether or not the examinee is in motion; analyzing the physiological parameters to determine whether or not each physiological parameter is in compliance with a normal physiological standard preinstalled in the monitoring apparatus if the examinee is determined not in motion, and also determining whether or not each physiological parameter is in compliance with a normal physiological standard preinstalled in the monitoring apparatus; and issuing a first precaution reporting signal to an identified recipient and sending out the first precaution reporting signal via a wireless transmission, if the physiological parameters are incompliance with the normal physiological standards.

摘要翻译： 在全面监测人体生理参数和安全状况的方法中，将该方法应用于佩戴在受检者体内的监测装置，其特征在于包括以下步骤：监测受检者当前的多个生理参数和多个运动信息; 分析运动信息以确定受检者是否运动; 分析生理参数，以确定每个生理参数是否符合预先安装在监测装置中的正常生理学标准，如果被检查者不被运动，并且还确定每个生理参数是否符合正常生理学 监测装置中预先安装标准; 以及如果所述生理参数不符合正常生理标准，则通过无线传输向所识别的接收方发出第一预警报告信号并发出所述第一预警报告信号。

公开(公告)号：US20080069169A1

公开(公告)日：2008-03-20

申请号：US11827003

申请日：2007-07-10

申请人： Peidong Wang ,  Chih-Cheng Lu ,  Daryoosh Vakhshoori

发明人： Peidong Wang ,  Chih-Cheng Lu ,  Daryoosh Vakhshoori

IPC分类号： H01S5/00 ,  H01L29/06 ,  H01L33/00

CPC分类号： B82Y20/00 ,  H01S5/028 ,  H01S5/06255 ,  H01S5/101 ,  H01S5/1057 ,  H01S5/34 ,  H01S5/3413 ,  H01S2301/04

摘要： Semiconductor substrate is disclosed having quantum wells having first bandgap, and quantum wells having second bandgap greater than first bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells having given bandgap, other quantum wells modified to bandgap greater than given bandgap. Semiconductor substrate is disclosed comprising wafer having quantum wells, section of first bandgap, and section of second bandgap greater than first bandgap. Method for forming semiconductor substrate is provided, comprising providing wafer having given bandgap, depositing dielectric cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap. Semiconductor structure is disclosed comprising substrate having quantum wells modified by depositing cap and rapid thermal annealing to tuned bandgap greater than given bandgap. Method for forming semiconductor substrate is disclosed, comprising providing wafer having quantum wells having given bandgap, depositing cap on portion and rapid thermal annealing to tuned bandgap greater than given bandgap.

摘要翻译： 公开了具有量子阱具有第一带隙的半导体衬底，并且具有大于第一带隙的第二带隙的量子阱。 公开了半导体结构，其包括具有给定带隙的量子阱的衬底，其他量子阱被修改为具有大于给定带隙的带隙。 公开了半导体衬底，其包括具有量子阱的晶片，第一带隙的截面以及大于第一带隙的第二带隙的截面。 提供了形成半导体衬底的方法，其包括提供具有给定带隙的晶片，在部分上沉积介电帽和快速热退火至大于给定带隙的调谐带隙。 公开了半导体结构，其包括具有通过沉积帽和快速热退火而修改的量子阱的衬底，所述量子阱具有大于给定带隙的调谐带隙。 公开了一种用于形成半导体衬底的方法，其包括提供具有给定带隙的量子阱的晶片，将部分上的沉积帽和快速热退火至大于给定带隙的调谐带隙。

公开(公告)号：US07098116B2

公开(公告)日：2006-08-29

申请号：US10753816

申请日：2004-01-08

申请人： Chih-Cheng Lu ,  Chuan-Ping Hou ,  Chu-Yun Fu ,  Chang Wen ,  Jang Syun Ming

发明人： Chih-Cheng Lu ,  Chuan-Ping Hou ,  Chu-Yun Fu ,  Chang Wen ,  Jang Syun Ming

IPC分类号： H01L21/76

CPC分类号： H01L21/02164 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31612 ,  H01L21/76229

摘要： A method of reducing oxide thickness variations in a STI pattern that includes both a dense trench array and a wide trench is described. A first HDP CVD step with a deposition/sputter (D/S) ratio of 9.5 is used to deposit a dielectric layer with a thickness that is 120 to 130% of the shallow trench depth. An etch back is performed in the same CVD chamber with NF3, SiF4 or NF3 and SiF4 to remove about 40 to 50% of the initial dielectric layer. A second HDP CVD step with a D/S ratio of 16 deposits an additional thickness of dielectric layer to a level that is slightly higher than after the first deposition. The etch back and second deposition form a smoother dielectric layer surface which enables a subsequent planarization step to provide filled STI features with a minimal amount of dishing in wide trenches.

摘要翻译： 描述了一种降低包括密集沟槽阵列和宽沟槽的STI图案中的氧化物厚度变化的方法。 使用沉积/溅射（D / S）比为9.5的第一HDP CVD步骤沉积厚度为浅沟槽深度的120至130％的电介质层。 在具有NF 3，SiF 4或NF 3 Si和SiF 4的相同CVD室中进行回蚀刻， 以去除初始介电层的约40至50％。 D / S比为16的第二HDP CVD步骤将附加的电介质层的厚度沉积到稍高于第一次沉积后的水平。 回蚀刻和第二沉积形成较平滑的介电层表面，其使得随后的平坦化步骤能够在宽的沟槽中提供最少量的凹陷的填充的STI特征。

公开(公告)号：US07043292B2

公开(公告)日：2006-05-09

申请号：US10176944

申请日：2002-06-21

申请人： Peter P. Tarjan ,  Chih-Cheng Lu ,  Walter Besio

发明人： Peter P. Tarjan ,  Chih-Cheng Lu ,  Walter Besio

IPC分类号： A61B5/402

CPC分类号： A61B8/483 ,  A61B5/0408 ,  A61B5/745 ,  A61B8/08 ,  A61B8/488

摘要： The method of presenting concurrent information about the electrical and mechanical activity of the heart using non-invasively obtained electrical and mechanical cardiac activity data from the chest or thorax of a patient comprises the steps of: placing at least three active Laplacian ECG sensors at locations on the chest or thorax of the patient; where each sensor has at least one outer ring element and an inner solid circle element, placing at least one ultrasonic sensor on the thorax where there is no underlying bone structure, only tissue, and utilizing available ultrasound technology to produce two or three-dimensional displays of the moving surface of the heart and making direct measurements of the exact sites of the sensors on the chest surface to determine the position and distance from the center of each sensor to the heart along a line orthogonal to the plane of the sensor and create a virtual heart surface; updating the measurements at a rate to show the movement of the heart's surface; monitoring at each ultrasonic sensor site and each Laplacian ECG sensor site the position and movement of the heart and the passage of depolarization wave-fronts in the vicinity; treating those depolarization wave-fronts as moving dipoles at those sites to create images of their movement on the image of the beating heart's surface; and, displaying the heart's electrical activity on the dynamically changing image of the heart's surface with the goal to display an approximation of the activation sequence on the beating virtual surface of the heart

摘要翻译： 使用来自患者的胸部或胸部的非侵入式获得的电和机械心脏活动数据呈现关于心脏的电和机械活动的并发信息的方法包括以下步骤：将至少三个有源拉普拉斯ECG心电图传感器放置在 患者的胸部或胸部; 其中每个传感器具有至少一个外环元件和内部实心圆形元件，将至少一个超声波传感器放置在胸部上，其中没有下面的骨结构，仅包括组织，并且利用可用的超声技术来产生二维或三维显示 的心脏的移动表面，并直接测量胸部表面上传感器的精确位置，以确定沿着与传感器平面垂直的线的每个传感器的心脏到心脏的位置和距离，并创建一个 虚拟心脏表面; 以显示心脏表面运动的速率更新测量值; 在每个超声波传感器位置和每个拉普拉斯ECG点位置监测心脏的位置和运动以及去极化波前的附近; 将这些去极化波前作为移动偶极子处理，以在心跳表面上形成运动图像; 并且在心脏表面的动态变化的图像上显示心脏的电活动，目的是显示心跳的虚拟表面上的激活序列的近似值

公开(公告)号：US20050153519A1

公开(公告)日：2005-07-14

申请号：US10753816

申请日：2004-01-08

申请人： Chih-Cheng Lu ,  Chuan-Ping Hou ,  Chu-Yun Fu ,  Chang Wen ,  Jang Ming

发明人： Chih-Cheng Lu ,  Chuan-Ping Hou ,  Chu-Yun Fu ,  Chang Wen ,  Jang Ming

IPC分类号： H01L21/3105 ,  H01L21/311 ,  H01L21/316 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/02164 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/31612 ,  H01L21/76229

摘要： A method of reducing oxide thickness variations in a STI pattern that includes both a dense trench array and a wide trench is described. A first HDP CVD step with a deposition/sputter (D/S) ratio of 9.5 is used to deposit a dielectric layer with a thickness that is 120 to 130% of the shallow trench depth. An etch back is performed in the same CVD chamber with NF3, SiF4 or NF3 and SiF4 to remove about 40 to 50% of the initial dielectric layer. A second HDP CVD step with a D/S ratio of 16 deposits an additional thickness of dielectric layer to a level that is slightly higher than after the first deposition. The etch back and second deposition form a smoother dielectric layer surface which enables a subsequent planarization step to provide filled STI features with a minimal amount of dishing in wide trenches.

摘要翻译： 描述了一种降低包括密集沟槽阵列和宽沟槽的STI图案中的氧化物厚度变化的方法。 使用沉积/溅射（D / S）比为9.5的第一HDP CVD步骤沉积厚度为浅沟槽深度的120至130％的电介质层。 在具有NF 3，SiF 4或NF 3 Si和SiF 4的相同CVD室中进行回蚀刻， 以去除初始介电层的约40至50％。 D / S比为16的第二HDP CVD步骤将附加的电介质层的厚度沉积到稍高于第一次沉积后的水平。 回蚀刻和第二沉积形成较平滑的介电层表面，其使得随后的平坦化步骤能够在宽的沟槽中提供最少量的凹陷的填充的STI特征。