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    Positive and negative voltage level shifter circuit
    11.
    发明授权
    Positive and negative voltage level shifter circuit 有权
    正，负电压电平转换电路

    公开(公告)号：US07948810B1

    公开(公告)日：2011-05-24

    申请号：US12250021

    申请日：2008-10-13

    Applicant: Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

    Inventor： Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

    IPC: G11C7/00

    CPC classification number: G11C7/1078 ,  G11C7/1084 ,  H03K3/356052 ,  H03K3/356113

    Abstract: A level shifter includes a level shifter module that receives a first input signal having high and low states and at least one voltage supply signal, and that generates a latch control signal based on the high and low states of the first input signal. A latch module receives the latch control signal, a data input signal, and the at least one voltage supply signal. The latch module selectively stores data associated with the data input signal based on the latch control signal. The latch module selectively changes the at least one voltage supply signal from a first level to a second level and outputs the data according to the second level based on the latch control signal.

    Abstract translation: 电平移位器包括电平移位器模块，其接收具有高和低状态的第一输入信号和至少一个电压供应信号，并且基于第一输入信号的高和低状态产生锁存控制信号。 锁存模块接收锁存控制信号，数据输入信号和至少一个电压供应信号。 锁存模块基于锁存控制信号有选择地存储与数据输入信号相关联的数据。 闩锁模块有选择地将至少一个电压供给信号从第一电平改变到第二电平，并且基于锁存控制信号输出根据第二电平的数据。

    Program-and-erase method for multilevel nonvolatile memory
    13.
    发明授权
    Program-and-erase method for multilevel nonvolatile memory 有权
    多级非易失性存储器的编程和擦除方法

    公开(公告)号：US07746704B1

    公开(公告)日：2010-06-29

    申请号：US12209794

    申请日：2008-09-12

    Applicant: Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

    Inventor： Qiang Tang ,  Bo Wang ,  Chih-Hsin Wang

    IPC: G11C16/04

    CPC classification number: G11C11/5621 ,  G11C16/10

    Abstract: A system includes an input that receives a control signal and a program module that initializes a nonvolatile multilevel memory cell based on the control signal. The program module initializes the nonvolatile multilevel memory cell by programming the nonvolatile multilevel memory cell to one of S states of the nonvolatile multilevel memory cell, where S is an integer greater than 1. The one of the S states is different than a lowest one of the S states.

    Abstract translation: 系统包括接收控制信号的输入端和基于控制信号初始化非易失性多电平存储单元的程序模块。 程序模块通过将非易失性多级存储器单元编程为非易失性多级存储器单元的S状态之一来初始化非易失性多级存储器单元，其中S是大于1的整数.S状态中的一个不同于 S州。

    Auto-zero current sensing amplifier
    14.
    发明授权
    Auto-zero current sensing amplifier 有权
    自动零电流检测放大器

    公开(公告)号：US07724596B1

    公开(公告)日：2010-05-25

    申请号：US12209577

    申请日：2008-09-12

    Applicant: Pantas Sutardja ,  Yonghua Song ,  Bo Wang ,  Chih-Hsin Wang ,  Qiang Tang

    Inventor： Pantas Sutardja ,  Yonghua Song ,  Bo Wang ,  Chih-Hsin Wang ,  Qiang Tang

    IPC: G11C7/02 ,  H03F3/45

    CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C2207/063

    Abstract: A sensing amplifier for a memory cell comprises a selection stage that outputs one of a reference current and a memory cell current during a first period and the other of the reference current and the memory cell current during a second period. The first period and the second period are non-overlapping. An input stage generates a first current based on the one of the reference current and the memory cell current during the first period and generates a second current based on the other of the reference current and the memory cell current during the second period. A sensing stage senses a first value based on the first current and stores the first value during the first period, senses a second value based on the second current during the second period and compares the first value to the second value.

    Abstract translation: 用于存储单元的感测放大器包括选择级，其在第一时段期间输出参考电流和存储单元电流之一，并且在第二时段期间输出参考电流和存储单元电流中的另一个。 第一期与第二期不重叠。 输入级在第一时段期间基于参考电流和存储单元电流之一产生第一电流，并且在第二周期期间基于参考电流和存储单元电流中的另一个产生第二电流。 感测级基于第一电流感测第一值并且在第一周期期间存储第一值，在第二周期期间基于第二电流感测第二值，并将第一值与第二值进行比较。

    ALIGNMENT PROTECTION IN NON-VOLATILE MEMORY AND ARRAY
    16.
    发明申请
    ALIGNMENT PROTECTION IN NON-VOLATILE MEMORY AND ARRAY 审中-公开
    非易失性存储器和阵列中的对准保护

    公开(公告)号：US20080237696A1

    公开(公告)日：2008-10-02

    申请号：US11933377

    申请日：2007-10-31

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H01L29/786

    CPC classification number: H01L27/11568 ,  G11C16/0416 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11534 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    Abstract: A memory device, a memory array and a method of arranging memory devices and arrays. The memory device includes a memory region including a plurality of memory cells, each memory cell with a source, a drain and a channel between the source and the drain, a channel dielectric, a charge storage region and an electrically alterable conductor-material system in proximity to the charge storage region. The memory device includes a plurality of conductor lines. The memory includes a non-memory region having embedded logic including a plurality of transistors, each transistor for electrically coupling one of the conductor lines and each transistor including a transistor source, a transistor drain and a transistor gate.

    Abstract translation: 存储器件，存储器阵列和布置存储器件和阵列的方法。 存储器件包括存储器区域，其包括多个存储器单元，每个存储单元具有源极，漏极和源极与漏极之间的沟道，沟道电介质，电荷存储区域和电可改变的导体材料系统 靠近电荷存储区域。 存储器件包括多条导体线。 存储器包括具有包括多个晶体管的嵌入逻辑的非存储区域，用于电耦合导体线之一的每个晶体管和包括晶体管源，晶体管漏极和晶体管栅极的每个晶体管。

    Low power electrically alterable nonvolatile memory cells and arrays
    17.
    发明申请
    Low power electrically alterable nonvolatile memory cells and arrays 有权
    低功率电气可变非易失性存储器单元和阵列

    公开(公告)号：US20080061321A1

    公开(公告)日：2008-03-13

    申请号：US11978875

    申请日：2007-10-30

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H01L21/336 ,  H01L21/82 ,  H01L27/10

    CPC classification number: H01L27/11568 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/26586 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/47 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    Abstract: A method of providing a memory cell includes providing a body of a semiconductor material having a first conductivity type, arranging a filter of a conductor-filter system in contact with a first conductor of the conductor-filter system, arranging at least portion of a second conductor of a conductor-insulator system in contact with the filter, arranging a first insulator of the conductor-insulator system in contact with the second conductor at an interface, arranging a first region spaced from the second conductor, arranging a channel of the body between the first region and the second conductor, arranging a second insulator adjacent to the first region, arranging a charge storage region between the first and the second insulators, arranging a first portion of a word-line adjacent to and insulated from the charge storage region, and arranging a second portion of the word-line adjacent to and insulated from the body.

    Abstract translation: 提供存储单元的方法包括提供具有第一导电类型的半导体材料的主体，布置与导体过滤器系统的第一导体接触的导体过滤系统的滤波器，将至少部分第二导体 与过滤器接触的导体 - 绝缘体系统的导体，在接口处布置导体 - 绝缘体系统的第一绝缘体与第二导体接触，布置与第二导体间隔开的第一区域，将主体的沟道布置在 所述第一区域和所述第二导体布置与所述第一区域相邻的第二绝缘体，在所述第一绝缘体和所述第二绝缘体之间布置电荷存储区域，布置与所述电荷存储区域相邻并与所述电荷存储区域绝缘的字线的第一部分， 并且将所述字线的第二部分布置成与所述主体相邻并且与所述主体绝缘。

    INVERTER NON-VOLATILE MEMORY CELL AND ARRAY SYSTEM
    18.
    发明申请
    INVERTER NON-VOLATILE MEMORY CELL AND ARRAY SYSTEM 有权
    逆变器非易失性存储器单元和阵列系统

    公开(公告)号：US20070263456A1

    公开(公告)日：2007-11-15

    申请号：US11748541

    申请日：2007-05-15

    Applicant: Bin Wang ,  Chih-Hsin Wang ,  William Colleran

    Inventor： Bin Wang ,  Chih-Hsin Wang ,  William Colleran

    IPC: G11C16/04

    CPC classification number: G11C16/10

    Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate and a four transistor storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

    Abstract translation: NVM阵列包括包括浮动栅极和四晶体管存储元件的NVM单元的行和列。 在编程和擦除模式期间，所选存储元件的电源电压关闭。 可以使用每个NVM单元或每行NVM单元的隔离晶体管来控制电源电压。

    Electrically alterable non-volatile memory cell
    20.
    发明授权
    Electrically alterable non-volatile memory cell 失效
    电可变非易失性存储单元

    公开(公告)号：US07098499B2

    公开(公告)日：2006-08-29

    申请号：US10919555

    申请日：2004-08-16

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC classification number: G11C16/14 ,  G11C16/0416 ,  H01L29/42332 ,  H01L29/7885 ,  H01L29/792

    Abstract: A nonvolatile memory cell is provided. The memory cell includes a storage transistor and an injector in a well of an n-type conductivity. The well is formed in a semiconductor substrate of a p-type conductivity. The storage transistor comprises a source, a drain, a channel, and a charge storage region. The source and the drain are formed in the well and having the p-type conductivity with the channel of the well defined therebetween. The charge storage region is disposed over and insulated from the channel region by an insulator. Further provided are methods operating the memory cell, including means for injecting electrons from the channel through the insulator onto the charge storage region and means for injecting holes from the injector through the well through the channel through the insulator onto the charge storage region. The memory cell can be implemented in a conventional logic CMOS process.

    Abstract translation: 提供非易失性存储单元。 存储单元包括n型导电性阱中的存储晶体管和注入器。 该阱形成在p型导电性的半导体衬底中。 存储晶体管包括源极，漏极，沟道和电荷存储区域。 源极和漏极形成在阱中并且具有p型导电性，阱之间的沟道被限定。 电荷存储区域通过绝缘体设置在沟道区域的上方并与绝缘体绝缘。 还提供了操作存储单元的方法，包括用于将电子从通道中通过绝缘体注入到电荷存储区域上的装置，以及用于将来自注射器的孔穿过阱通过穿过绝缘体的沟槽注入到电荷存储区上的装置。 存储器单元可以在传统的逻辑CMOS工艺中实现。

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